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Embedded Systems Engineering Curriculum
·
Module 4
CPU and System Architecture
1
Cache Hierarchy: L1, L2, L3 Explained
Explain the L1/L2/L3 cache hierarchy, including cache lines, sets, ways, and associativity.
2
Cache Coherency in DMA and Multi-Core Systems
Analyze cache coherency issues in DMA and multi-core contexts, explaining why cache flush/invalidation is required.
3
Paging, TLBs, and Memory Translation Performance
Describe virtual-to-physical address translation via paging and the role of the TLB, analyzing the performance impact of misses.
4
RISC Pipeline: Hazards and Solutions
Explain the classic RISC instruction pipeline and identify the causes and effects of structural, data, and control hazards.
5
Branch Prediction Strategies
Compare static vs. dynamic branch prediction strategies and their role in mitigating control hazard penalties.
6
RISC vs. CISC: ARM and x86 in Semiconductor Design
Compare RISC vs. CISC architectures with concrete ARM vs. x86 examples relevant to semiconductor roles.
7
SMP vs. AMP: Multi-Core Architectures Explained
Compare SMP vs. AMP multi-core architectures and their implications for scheduling, communication, and cache coherency.
8
ARM TrustZone and Secure Boot Explained
Explain ARM TrustZone architecture and the secure boot chain of trust from boot ROM to application.
Previous module
The Build Process and Program Execution
Next module
Embedded Data Structures and Algorithms