MOSFET DC Operating Point with Active Load

Introduction

In our previous lesson, we established a systematic method for finding the DC operating point (Q-point) in MOSFET circuits with passive resistors and ideal current sources. We saw that proper biasing is essential to prepare a transistor for amplification. Today, we will explore a technique that is fundamental to modern integrated circuit (IC) design: replacing bulky resistors with other transistors. Your learning goal is to analyze the DC operating point of a MOSFET circuit that uses another transistor as its load—a configuration known as an active load.

This is a crucial step in your study of analog circuits. In the world of microelectronics, where millions of transistors fit on a tiny silicon chip, a single resistor can be a space-hogging component. Using transistors as active loads not only saves precious chip area but, as we will see in later modules, also enables the design of amplifiers with exceptionally high voltage gain. This lesson will equip you with the analytical skills to determine the Q-point for these sophisticated and practical circuits.

Why Use Active Loads?

Before diving into the analysis, it's important to understand the motivation behind using a transistor as a load. In discrete circuits built on a breadboard, using a resistor is simple and effective. However, in an IC, the story is very different.

The key takeaway is that active loads are a cornerstone of modern analog IC design. They are more area-efficient and can provide much higher incremental resistance than a passive resistor, which is the key to achieving high voltage gain. Let's look at a practical justification.

This practical constraint makes passive resistors unsuitable for high-gain stages in ICs. The solution is to use a transistor, biased to behave like a current source, as the load.

Analyzing a Common-Source Amplifier with an Active Load

The most common active load configuration is a PMOS current mirror acting as a load for an NMOS common-source amplifier. Let's break down how to analyze its DC operating point.

The circuit shown above is a differential pair, but we can analyze one half of it (e.g., transistors Q1 and Q3) to understand the principles of a single common-source stage with an active load. Q3 is part of a current mirror, and it is biased to provide a specific DC current to the drain of the amplifying transistor, Q1.

The DC analysis hinges on one key principle: the drain current of the amplifying transistor must equal the current supplied by the load transistor.

$$I_{D,\text{NMOS}}=I_{D,\text{PMOS}}$$

Our goal is to find the DC output voltage, $V_{OQ}$, and confirm the required input DC voltage, $V_{GSQ}$, that establishes the desired drain current, $I_{DQ}$, while ensuring both transistors remain in the saturation region.

The following video provides a concise explanation of these operating conditions.

As the video explains, for the circuit to function correctly as an amplifier, both transistors must be in saturation. This imposes two critical conditions on the DC output voltage, $V_O$:

1. For the NMOS amplifier (M1) to be in saturation: The drain-source voltage must be greater than its overdrive voltage.
   $V_{DS1}\ge V_{GS1}-V_{TN}$
   Since $V_{DS1}=V_O$, this sets the lower limit for the output voltage:
   $V_{O,\text{min}}=V_{GS1}-V_{TN}$

2. For the PMOS load (M2) to be in saturation: Its drain-source voltage, $V_{SD2}$, must be greater than its overdrive voltage.
   $V_{SD2}\ge V_{SG2}-|V_{TP}|$
   Since $V_{SD2}=V_{DD}-V_O$, this can be rearranged to find the upper limit for the output voltage:
   $V_O\le V_{DD}-(V_{SG2}-|V_{TP}|)$
   So, $V_{O,\text{max}}=V_{DD}-(V_{SG2}-|V_{TP}|)$.

The DC operating point $V_{OQ}$ must lie within this valid range: $V_{O,\text{min}}\le V_{OQ}\le V_{O,\text{max}}$.

A Step-by-Step Analysis Example

Let's apply these concepts to a concrete problem. The procedure is an extension of the five-step method from our last lesson. We'll assume both transistors are in saturation, equate their drain currents, and solve for the unknown voltages.

We'll use a slightly different circuit configuration to broaden your experience, but the core principles are identical. In this problem, an NMOS current mirror sources current into a pair of series-connected NMOS transistors.

The key insight from this problem is that once you know the DC bias current, the rest of the analysis involves applying the saturation I-V equation and basic circuit laws (KVL, KCL). The fact that the load is an active transistor simply means its current is determined by its own $V_{GS}$ and device parameters, rather than by Ohm's law through a resistor.

Let's consider one more detailed example, which is very typical of a university exam question.

The problem asks to design the circuit, but we can use it for an analysis exercise. Let's assume we are given that the bias current $I_Q=200\mu A$. In a differential pair, this current splits equally, so the quiescent drain current for each branch is $I_{D1}=I_{D2}=I_Q/2=100\mu A$.

The circuit has PMOS transistors M3 and M4 forming a current mirror load for NMOS transistors M1 and M2. To find the Q-point of the right-hand side (M2 and M4), we proceed as follows:

1. Assume Saturation: Assume M2 and M4 are in saturation.
2. Enforce Currents: We know $I_{D2}=I_{D4}=100\mu A$.
3. Analyze PMOS Load: For the PMOS transistor M4, we have:
   $I_{D4}=\frac{1}{2}{K}_p(V_{SG4}-|V_{TP}|{)}^2$
   With $K_p=250\mu A/V^2$, $|V_{TP}|=1.0V$, and $I_{D4}=100\mu A$, we can solve for $V_{SG4}$.
   $100\times 10^{-6}=\frac{1}{2}(250\times 10^{-6})(V_{SG4}-1.0{)}^2$
   $0.8=(V_{SG4}-1.0{)}^2⟹V_{SG4}-1.0=\sqrt{0.8}\approx 0.894$
   $V_{SG4}\approx 1.894V$
4. Analyze NMOS Amplifier: For the NMOS transistor M2, we have:
   $I_{D2}=\frac{1}{2}{K}_n(V_{GS2}-V_{TN}{)}^2$
   With $K_n=500\mu A/V^2$, $V_{TN}=2.0V$, and $I_{D2}=100\mu A$, we can solve for $V_{GS2}$.
   $100\times 10^{-6}=\frac{1}{2}(500\times 10^{-6})(V_{GS2}-2.0{)}^2$
   $0.4=(V_{GS2}-2.0{)}^2⟹V_{GS2}-2.0=\sqrt{0.4}\approx 0.632$
   $V_{GS2}\approx 2.632V$
   This $V_{GS2}$ is the required DC gate-source voltage at the input to set the desired 100 $\mu$A current. The Q-point current is $I_{DQ}=100\mu A$. The Q-point output voltage, $V_{OQ}=V_{DS2}$, would depend on the supply voltages $V^{+}$ and $V^{-}$, which are not given here, but this process demonstrates how the transistor currents and voltages are linked.

Conclusion

In this lesson, you have moved from analyzing circuits with simple passive loads to understanding the DC behavior of amplifiers with active loads. This is a significant step towards mastering the design of modern integrated circuits.

Here are the main takeaways:

• Active loads (transistors used as loads) are preferred in ICs to save space and enable high-gain amplifier designs.
• A common implementation is a PMOS current mirror loading an NMOS amplifying transistor.
• DC analysis is centered on the principle of equating the drain currents of the amplifier and load transistors ($I_{D,\text{amp}}=I_{D,\text{load}}$).
• To find the Q-point and valid operating range, you must apply the saturation conditions for both the amplifying and the load transistors, which defines the allowable swing for the DC output voltage.

In our next lesson, we will pivot from analysis to design. Armed with the ability to determine the Q-point of a given circuit, you will learn how to choose the component values and transistor sizes needed to achieve a specific, desired DC operating point, a core skill for any circuit designer.