VLSI Engineering

Distinguish the behavior of level-sensitive latches from edge-triggered flip-flops.

Determine whether a flip-flop interface meets setup, hold, and clock-to-Q timing requirements.

Derive next-state equations for a register-based sequential circuit.

Design a synchronous binary counter with enable and reset controls.

Design a configurable shift register from a timing specification.

Translate a sequential behavior specification into a finite-state diagram and state table.

Select Moore or Mealy output logic for a stated design requirement.

Analyze the startup behavior of a sequential circuit under synchronous and asynchronous reset.

Configure Icarus Verilog or Verilator, GTKWave, and Yosys on Windows or Linux for command-line use.

Differentiate preprocessing, compilation, elaboration, simulation, and synthesis in an RTL workflow.

Declare SystemVerilog modules with scalar, vector, input, output, and parameter ports.

Use SystemVerilog literals, packed logic types, widths, and signedness correctly.

Translate a logic equation into a SystemVerilog expression using the appropriate operators.

Instantiate modules and connect hierarchical ports without width or direction mismatches.

Compile and simulate a simple SystemVerilog design from the command line.

Inspect signal values and timing relationships in a GTKWave waveform.

Describe combinational logic using continuous assignments.

Code complete combinational behavior with always_comb, if, and case statements.

Identify and correct unintended latch inference in a combinational RTL block.

Predict the result width and signedness of a SystemVerilog arithmetic expression.

Create a parameterized combinational module with compile-time width checks.

Use generate constructs to replicate or conditionally elaborate hardware.

Encapsulate reusable combinational calculations in SystemVerilog functions.

Implement and lint a parameterized arithmetic logic unit from an opcode specification.

Use always_ff and nonblocking assignments to model clocked hardware.

Implement registers with specified reset, enable, and load priorities.

Implement a programmable counter or timer without off-by-one errors.

Code a shift register and pulse generator from cycle-accurate requirements.

Implement a finite-state machine using separate state-register and next-state logic.

Partition a small sequential design into controller and datapath blocks.

Implement clock-enable behavior without creating a derived or gated clock.

Use lint diagnostics to correct common sequential RTL coding defects.

Construct a SystemVerilog testbench with a design-under-test instance and controlled simulation lifecycle.

Generate repeatable clock and reset stimulus in a testbench.

Use tasks to apply directed transactions to a design under test.

Create a reference calculation that automatically checks observed outputs.

Write immediate and concurrent assertions for cycle-level design properties.

Generate reproducible randomized stimulus for input corner cases.

Define functional coverage points for a small RTL block.

Diagnose unknown values, race conditions, and functional failures using logs and waveforms.

Calculate latency, initiation interval, and throughput for a synchronous datapath.

Insert pipeline registers to divide a long combinational path while preserving functionality.

Propagate valid information through a fixed-latency pipeline.

Implement a ready/valid transfer interface that remains stable under backpressure.

Design a multiport register file with specified read and write behavior.

Infer a synchronous ROM or RAM from portable SystemVerilog RTL.

Derive pointer, empty, and full logic for a synchronous FIFO.

Implement and verify a parameterized synchronous FIFO.

Define a memory-mapped register set from software-visible control and status requirements.

Implement address decoding, write strobes, and read-data multiplexing for a register bank.

Interpret transfer timing and control signals for the AMBA APB protocol.

Implement an APB slave interface for a memory-mapped register bank.

Calculate UART divider values and identify the fields of a UART frame.

Implement a configurable UART transmitter.

Implement a UART receiver with synchronized input and midpoint sampling.

Connect an APB register bank to UART control and status signals.

Identify unsafe single-bit and multi-bit clock-domain crossings in an RTL design.

Explain how metastability risk depends on settling time, clock rate, and data transition rate.

Implement a two-flop synchronizer for a slowly changing single-bit signal.

Transfer a one-cycle event across clock domains using a toggle synchronizer.

Transfer control and data coherently across clock domains using a request-acknowledge handshake.

Use Gray-coded counters to reduce ambiguity when transferring changing multi-bit state.

Explain how synchronized pointers establish full and empty status in an asynchronous FIFO.

Implement reset assertion and synchronized deassertion for each clock domain.

Synthesize a SystemVerilog design with Yosys and inspect the generated netlist.

Interpret synthesis warnings and resource reports to confirm the inferred hardware.

Identify simulation-only constructs and common causes of simulation-synthesis mismatch.

Define clock, input-delay, and output-delay constraints for a synchronous interface.

Read a static timing report and identify launch, capture, data, and clock paths.

Diagnose setup and hold violations from timing slack and path details.

Choose an RTL change that improves a specified timing or area bottleneck.

Run lint, synthesis, and timing checks as a repeatable quality-gate script.

Map RTL structures to FPGA lookup tables, flip-flops, block RAMs, carry chains, and DSP blocks.

Create clock and I/O constraints for a small FPGA top-level design.

Run synthesis and place-and-route for a supported FPGA target without physical hardware.

Interpret FPGA utilization, timing, and implementation reports.

Explain how ASIC standard cells implement combinational and sequential RTL.

Trace the artifacts produced by an ASIC flow from RTL synthesis through layout generation.

Interpret area, timing, and power summaries for a small ASIC block.

Compare FPGA and ASIC implementation trade-offs for the same RTL architecture.

Write a cycle-accurate feature specification and register map for an APB-controlled UART subsystem.

Partition the UART subsystem into interfaces, control logic, FIFOs, datapaths, and status logic.

Implement the subsystem's APB register and interrupt behavior.

Integrate the UART transmitter, receiver, and FIFOs into the subsystem.

Create a verification plan covering normal operation, backpressure, reset, overflow, and framing errors.

Build a self-checking subsystem testbench with assertions and randomized transactions.

Run lint, synthesis, and timing checks and resolve all high-severity findings.

Document the design, verification evidence, implementation results, and architectural trade-offs as a portfolio project.