Designing Bit-Level Adders and Subtractors

Hello! Last lesson, you used a truth table to decide how a multiplexer should be wired. This lesson uses the same design discipline for arithmetic: specify what each bit position must produce, derive logic for that position, and connect positions to make a multi-bit circuit.

You’ll build a full adder from its bit-level behavior, use it in a four-bit adder, and then make the same hardware perform subtraction. The result is a circuit whose outputs have precise meanings—an essential habit when you later describe arithmetic hardware in RTL.

Start with one bit position

A single bit position cannot hold the value 2. When two input bits are both 1, their sum is binary $10$: the sum bit is 0, and a carry bit of 1 belongs in the next position.

A half adder implements the case with two inputs and no incoming carry:

The sum is 1 when exactly one input is 1; the carry is 1 when both are 1. Thus the two output functions are $S=X\oplus Y$ and $C_{\text{out}}=XY$. One XOR gate and one AND gate realize this specification.

Watch the opening of Combinational Devices 1: Half Adder and Full Adder from Down to the Wires. It develops the half adder from binary addition, then shows why its missing carry input matters when adding multi-bit values.

A half adder is useful at a position known to have no carry-in. For a reusable stage in a multi-bit adder, however, carry-in must be an input, not an assumption.

Design a full-adder stage

A full adder has three one-bit inputs: operand bits $X$ and $Y$, and an incoming carry $C_{\text{in}}$. Its two outputs must satisfy this numerical specification:

The right-hand side expresses the result as a bit at the current position plus a carry worth two at the next position. Since three input bits can total 0, 1, 2, or 3, one sum bit and one carry bit cover every case.

Two patterns turn this table into gates. The sum is 1 when an odd number of inputs are 1. The carry is 1 when at least two inputs are 1. Define $P=X\oplus Y$; then:

The carry equation separates two reasons for a carry. If $X=Y=1$, the stage generates a carry regardless of its carry-in. If exactly one of $X,Y$ is 1, an incoming carry passes through. These equations specify one straightforward gate implementation: form $P$ with XOR, use it for the sum and one carry term, then OR the two carry terms.

Continue the same video to see the three-input truth table and the derivation of both output functions. You have already used Karnaugh maps, so concentrate on how the resulting logic matches the arithmetic specification rather than on map mechanics alone.

The numerical specification is also a compact way to check a proposed design. For example, inputs $X=1$, $Y=0$, $C_{\text{in}}=1$ total 2. The outputs must therefore be $S=0$, $C_{\text{out}}=1$—not merely whichever values a plausible-looking gate arrangement happens to produce.

Connect stages into a four-bit adder

Let $A_3{A}_2{A}_1{A}_0$ and $B_3{B}_2{B}_1{B}_0$ be four-bit operands, with index 0 denoting the least significant bit. Give stage $i$ inputs $A_i$, $B_i$, and $C_i$. It produces result bit $S_i$ and carry $C_{i+1}$. For ordinary addition without an incoming carry, set $C_0=0$.

The key connection is that each stage’s carry-out supplies the next stage’s carry-in. This is a ripple-carry adder: even though all operand bits are presented together, an upper stage may need the carry calculated by a lower stage.

The video gives a brief view of the connected stages:

For a concrete trace, add $A=0111$ and $B=0011$. At bit 0, $1+1+0$ produces $S_0=0,C_1=1$. At bit 1, $1+1+1$ produces $S_1=1,C_2=1$. At bit 2, $1+0+1$ produces $S_2=0,C_3=1$. Finally, bit 3 adds $0+0+1$, producing $S_3=1,C_4=0$. Reading the result in its usual order gives $S=1010$, or 10.

Specify the output width. Four-bit operands can produce a five-bit unsigned sum: $1111+0001$, for example, yields $C_4=1$ and $S=0000$. If the interface exposes only $S$, its four bits wrap to zero. If the interface exposes $C_4$ as well, the full result is $10000$. Neither behavior is inherently wrong; the circuit specification must say which result is required.

Reuse the adder for subtraction

A fixed-width subtractor need not implement borrowing as a separate chain of gates. Recall that, within four bits, the two’s complement of $B$ is formed by inverting its bits and adding 1. Thus the low four result bits of $A-B$ can be calculated by adding $A$, the bitwise complement of $B$, and an initial carry of 1.

Watch the subtraction explanation in 4-bit Adder and Subtractor Circuit Explained from ALL ABOUT ELECTRONICS. It shows why the inversion and the added 1 are both necessary.

To make one circuit perform either operation, introduce a mode input $K$. Feed each $B_i$ through an XOR gate with $K$, and connect $K$ to the first stage’s carry-in:

Each full-adder stage now receives $A_i,Y_i,C_i$. The two modes follow directly from XOR behavior:

The mode must control both the XOR gates and $C_0$. Inverting $B$ without setting $C_0=1$ would leave the subtraction one too small.

Watch the video’s unified-circuit explanation, then inspect the supplied diagram.

In the diagram, follow the circuit from right to left: bit 0 is the rightmost full adder, and its carry feeds bit 1. The label $C_{\text{out}}$ at the left is the carry leaving bit 3. Setting $K=0$ passes all $B$ bits unchanged and starts with carry 0. Setting $K=1$ inverts all $B$ bits and starts with carry 1.

Interpret and check the outputs

The four result bits are the low four bits of the selected arithmetic operation. They do not, by themselves, say whether you intended an unsigned or signed two’s-complement interpretation.

Consider subtraction with $A=0101$ and $B=0011$. In subtraction mode, the adder receives $0101$, the inverted $B$ value $1100$, and initial carry 1. The result is $S=0010,C_4=1$: the low bits represent 2.

Reverse the operands: $A=0011$, $B=0101$. Now the result is $S=1110,C_4=0$. As a four-bit two’s-complement value, $1110$ represents $-2$. As an unsigned value, those same bits represent 14—the wrapped four-bit result. The operation and the chosen number interpretation determine what you report.

For unsigned subtraction in this design, the final carry has a useful status meaning: $C_4=1$ means no borrow ($A\ge B$); $C_4=0$ means a borrow was needed ($A<B$). During unsigned addition, $C_4$ instead indicates a carry beyond four bits. Do not label it simply “overflow” without defining the intended arithmetic. Signed overflow is a different condition: for example, four-bit signed $0111+0011$ produces $1010$, even though $7+3$ is outside the signed four-bit range of $-8$ through $7$. Here $C_4=0$, so carry-out alone would miss the signed overflow.

A sound bit-level design therefore states its contract before choosing gates: operand width, whether an incoming carry is allowed, which mode performs which operation, which result bits are retained, and whether carry, borrow, or signed-overflow status is required. The full-adder truth table establishes each stage’s behavior; checking representative cases such as a carry across several positions, a result beyond four bits, and subtraction in both operand orders establishes that the connections and output interpretation match that contract.

Key takeaways

A full adder turns three input bits into a sum bit and a carry bit according to $X+Y+C_{\text{in}}=S+2C_{\text{out}}$. Connecting its carry outputs to successive carry inputs produces a multi-bit ripple-carry adder. Conditional XOR gates on $B$, with the same mode signal used as the initial carry, let that adder compute either $A+B$ or $A-B$. Always define the result width and status-bit meaning alongside the logic.

Next, you’ll examine how long a combinational path takes to settle and why changing inputs can briefly produce glitches—particularly relevant when a carry must travel through several stages.