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High-Performance AI Computing
·
Module 2
CPU and Parallelism Fundamentals
1
Understanding the CPU Cycle: Fetch, Decode, Execute, and Pipelining
Describe the fetch-decode-execute cycle and the role of the modern CPU pipeline.
2
Understanding CPU Cache: Levels and Cache Lines
Explain the CPU cache hierarchy (L1/L2/L3) and the concept of a cache line.
3
Cache Performance and Data Access Patterns
Analyze how data access patterns (e.g., spatial and temporal locality) affect cache performance.
4
Exploiting Instruction-Level Parallelism: Pipelining and Superscalar Execution
Define instruction-level parallelism (ILP) and describe how pipelining and superscalar execution exploit it.
5
SIMD: The Power of Data Parallelism
Explain SIMD (Single Instruction, Multiple Data) and its role in modern data-parallel computation.
6
Amdahl's Law: Calculating Theoretical Speedup
State Amdahl's Law and calculate the theoretical speedup for a given parallelizable workload.
7
CPU vs. GPU: Latency vs. Throughput
Distinguish between latency-oriented (CPU) and throughput-oriented (GPU) processor design philosophies.
Previous module
C/C++ Systems Programming Foundations
Next module
Modern GPU Architecture