Introduction
In our last lesson, we traced the fetch-decode-execute cycle for a simple program. We saw how the CPU executes instructions like LDA (Load), ADD (Add), and STA (Store) one by one. These are small, fundamental operations. This naturally leads to a crucial question in computer architecture: what is the best "vocabulary" for a CPU? Should it be composed of many simple, fast words, or fewer, but more powerful and descriptive ones?
This question is at the heart of two competing design philosophies for Instruction Set Architectures (ISAs). This lesson will explore this fundamental trade-off. Our learning outcome is to distinguish between RISC and CISC instruction set architectures. We'll examine their core principles, compare their characteristics, and see how this historical debate shapes the processors we use every day, from smartphones to supercomputers.
The Two Philosophies: A Tale of Two Compilers
Imagine you have to give someone instructions to assemble a piece of furniture. You could either:
- Give a series of very simple, atomic instructions: "Pick up screw A. Insert screw A into hole B. Turn screwdriver clockwise three times."
- Give a single, more complex instruction: "Attach the leg to the tabletop."
This is the essence of the RISC vs. CISC debate.
- CISC (Complex Instruction Set Computer): This philosophy favors creating powerful, specialized instructions that can accomplish multi-step tasks (like "attach the leg") in a single go. The goal is to make the assembly language powerful, thus simplifying the compiler's job of translating high-level code (like C++) into machine instructions.
- RISC (Reduced Instruction Set Computer): This philosophy argues for a small set of simple, general-purpose instructions, each of which can be executed very quickly (in a single clock cycle). This puts more responsibility on the compiler to intelligently combine these simple steps to perform a complex task.
To see this in action, let's examine how each approach would handle a simple multiplication.
The following article from Stanford's CS department provides a clear, practical example of multiplying two numbers in memory using both CISC and RISC approaches. It perfectly illustrates the core philosophical difference.
Read the sections 'The CISC Approach' and 'The RISC Approach'. Pay close attention to the assembly code examples for the MULT operation and how they differ.
As you saw, the CISC approach uses a single MULT instruction that handles loading from memory, performing the calculation, and storing the result. In contrast, the RISC approach requires four separate instructions: LOAD, LOAD, PROD, and STORE.
At first glance, the CISC approach seems more efficient—one instruction versus four. However, that single MULT instruction is far more complex for the hardware to execute and may take many clock cycles. The four RISC instructions are simple and can be executed very quickly, often one per clock cycle, allowing for performance optimizations like pipelining, which we'll discuss in a future lesson.
Key Characteristics: A Head-to-Head Comparison
The philosophical difference we've just discussed leads to several concrete distinctions in the design and behavior of RISC and CISC processors. The following video provides a concise overview of these differences.
L-2.13: RISC vs CISC | Computer Organization & Architecture
This video from Gate Smashers breaks down the key differences between RISC and CISC across several important characteristics. It's a great way to build a mental checklist for comparing them.
Watch from 00:40 to 06:10. As you watch, focus on building a table of differences in your notes based on these categories: Instruction Set Size, Instruction Length, Addressing Modes, Clock Cycles per Instruction, Memory Access, and Control Unit type.
Let's consolidate those points into a clear comparison table.
| Feature | CISC (Complex Instruction Set Computer) | RISC (Reduced Instruction Set Computer) |
|---|---|---|
| Instruction Set | Large number of instructions, some highly specialized. | Small, optimized set of the most-used instructions. |
| Instruction Format | Variable-length instructions. This makes decoding complex as the CPU must first figure out how long the instruction is. | Fixed-length instructions. This simplifies the fetching and decoding process, which is ideal for pipelining. |
| Clock Cycles | Instructions are complex and often take multiple clock cycles to complete. | Simple instructions aim for completion in a single clock cycle. |
| Memory Access | Operations can directly manipulate memory (e.g., ADD mem_A, mem_B). Known as "memory-to-memory" operations. |
Only LOAD and STORE instructions access memory. All other operations (add, multiply, etc.) are register-to-register. |
| Control Unit | Typically uses a microprogrammed control unit. Complex instructions are sequences of micro-instructions stored in ROM. This is flexible but slower. | Typically uses a hardwired control unit. The logic is built directly into the circuitry, making it very fast but less flexible. |
| Compiler Role | Compiler does less work, as complex operations are mapped directly to single assembly instructions. | Compiler does more work, optimizing the sequence of simple instructions to perform a task efficiently. |
The following images visually summarize the last two points.
Is This Still a Thing? The Modern Reality
You might be wondering if this is just a historical debate. The answer is no, but the lines have blurred significantly. Early on, CISC dominated desktops (Intel's x86 architecture) while RISC found its home in workstations and servers. Today, RISC is ubiquitous in mobile devices (the ARM architecture in your phone), and modern CISC processors have adopted many RISC principles internally.
This next video does an excellent job of explaining the evolution and current state of the RISC vs. CISC world. It addresses the most important modern development: micro-operations.
RISC vs CISC - Is it Still a Thing?
This video by Gary Explains addresses the modern relevance of the RISC vs. CISC debate. It explains how today's CISC processors are not what they seem on the surface.
Watch the section from 07:00 to 11:09. Pay very close attention to the concept of 'micro-ops' and how modern Intel (x86) processors work internally. This is the key to understanding the modern landscape.
As the video explained, modern CISC processors like those from Intel and AMD don't execute complex x86 instructions directly. Instead, the first thing they do is break them down into simple, RISC-like instructions called micro-ops. These micro-ops are then fed into a highly optimized, RISC-style execution core that uses techniques like pipelining.
Why do this? Backward compatibility. It allows these processors to run decades' worth of software written for the x86 CISC instruction set, while leveraging the performance benefits of a RISC-like internal architecture.
So, while the "pure" CISC design is largely a thing of the past, the CISC instruction set remains dominant in desktops and servers. Meanwhile, RISC processors (primarily ARM) dominate the mobile and embedded markets due to their power efficiency and are rapidly expanding into laptops (like Apple's M-series chips) and data centers.
Conclusion
In this lesson, we explored the fundamental differences between RISC and CISC architectures. You learned that this is not just about the number of instructions, but a deep philosophical difference in where to place complexity: in the hardware or in the software.
Key Takeaways:
- CISC aims to simplify the compiler by providing complex, multi-cycle instructions that operate directly on memory. It features variable-length instructions and microprogrammed control.
- RISC aims to simplify the hardware with a small set of fixed-length, single-cycle instructions. It relies on a load-store architecture and a smart compiler to optimize performance.
- The key trade-off is between the number of instructions per program (lower in CISC) and the cycles per instruction (lower in RISC).
- In modern systems, the lines are blurred. Most CISC processors (like x86) use a RISC-like core internally, translating complex instructions into simpler micro-ops for execution.
Preview of the Next Lesson:
We've repeatedly mentioned the crucial role of the compiler in both architectures, especially in RISC. But how does a compiler actually work? How does it take the C++ code you write and turn it into the machine instructions that a CPU can understand? In the next lesson, we will describe the compilation pipeline: preprocessing, compiling, and assembling source code into object files. This will connect your C++ programming experience directly to the hardware concepts we're learning.