GEMM Optimization: From Naive to High-Performance

Implement a naive, thread-per-element matrix multiplication (GEMM) CUDA kernel.

Implement tiled matrix multiplication using shared memory to reduce global memory accesses.

Analyze the reduction in global memory traffic and performance improvement from shared memory tiling.

Implement register-level tiling within a shared memory tile to maximize data reuse from registers.

Use vectorized memory loads (e.g., `float4`) to increase memory bandwidth utilization.

Handle boundary conditions for matrices whose dimensions are not integer multiples of the tile size.

Benchmark each GEMM optimization stage against a library implementation (cuBLAS) and analyze remaining performance gaps.