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Chip design bootcamp preparation
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Module 6
Modeling Sequential Logic in Verilog
1
Modeling a Synchronous Reset D Flip-Flop with `always @(posedge clk)`
Model an edge-triggered D flip-flop with synchronous reset using `always @(posedge clk)`.
2
Blocking vs. Non-Blocking Assignments
Differentiate between blocking (`=`) and non-blocking (`<=`) assignments and their use cases.
3
Parameterized N-bit Register with Load Enable
Implement a parameterized N-bit register with a load enable signal.
4
Parameterized N-bit Synchronous Up-Counter with Enable
Implement a parameterized N-bit synchronous up-counter with an enable signal.
5
Parameterized N-Bit Shift Registers
Implement a parameterized N-bit shift register.
Previous module
Modeling Combinational Logic in Verilog
Next module
Finite State Machine (FSM) Design and Implementation