Parameterized N-bit Register with Load Enable

1. What is a Register and Why Does it Need an "Enable"?

At its core, a register is simply a collection of D flip-flops that share a common clock. Each flip-flop stores one bit, so an N-bit register uses N flip-flops to store an N-bit value.

But a simple register that just loads its input on every clock cycle has a major drawback. Imagine it's part of a larger system where many components share a common data bus. If our register is always listening, it will capture whatever random data happens to be on the bus at every clock tick. We need a way to tell the register, "Load the data on the bus now," and "Ignore the bus and hold your current value at all other times."

This is the job of the load enable signal.

To understand this problem more deeply, let's watch a couple of short video clips.

2. How the Load Enable Works: The Multiplexer

So, how do we implement this "hold" functionality? The solution is elegant: we place a 2-to-1 multiplexer before the data input of each flip-flop.

• The load signal acts as the multiplexer's select line.
• When load is 1, the multiplexer selects the external data input (d).
• When load is 0, the multiplexer selects the flip-flop's own current output (q).

This creates a feedback loop. By feeding the current output back to the input, the flip-flop simply re-loads the same value it already holds on the next clock edge.

The following video clip shows this exact circuit diagram.

So, the logic we need to model is:

• if (load == 1) q_next = d;
• else q_next = q_current;

3. Writing a Parameterized Register in Verilog

Now let's translate this concept into reusable Verilog code. A key goal in modern design is to write code once and use it many times. We achieve this with parameters.

Introducing Verilog parameter

A parameter is a constant within a Verilog module that can be changed (or "overridden") when you instantiate that module. This allows us to, for example, define a parameter N = 32 for data width, and then later create an 8-bit instance or a 64-bit instance from the same source code.

This reading from ChipVerify provides a concise and practical guide to using parameters.

The Verilog Code

Armed with the concepts of load enable logic and parameters, let's look at a clean, synthesizable implementation of our register. The code below defines a module for an N-bit register with a synchronous reset (reset) and a load enable (enable).

module Nbit_register #(
    parameter N = 32  // Default width is 32 bits
) (
    // Inputs
    input wire clk,
    input wire reset,
    input wire enable,
    input wire [N-1:0] d,

    // Output
    output reg [N-1:0] q
);

    always @(posedge clk) begin
        if (reset) begin
            q <= {N{1'b0}}; // Reset to all zeros
        end else if (enable) begin
            q <= d;         // Load new data from d
        end
        // If reset is 0 and enable is 0, q implicitly holds its value
    end

endmodule

Let's break this down:

1. module Nbit_register #(...);: This is the modern ANSI style for declaring a module with parameters.
2. parameter N = 32: We define our width parameter N and give it a default value of 32.
3. [N-1:0] d, [N-1:0] q: Notice how we use N to define the size of our data input and output. This is crucial for making the module parameterizable, as pointed out in the ChipVerify article.
4. always @(posedge clk): This is our sequential logic block. As per last lesson's rule, we will exclusively use non-blocking assignments (<=) inside.
5. if (reset): We include a synchronous reset. It's good practice to have a reset signal to force the register into a known state at the beginning. The syntax {N{1'b0}} is a Verilog replication operator; it means "replicate the bit 1'b0 N times," which creates a vector of N zeros.
6. else if (enable): This is the core of our load-enable logic. Only if reset is low and enable is high will the register load the value from d.
7. The Implicit "Hold": What happens if both reset and enable are low? Notice there is no final else statement. In a clocked always block, if a reg is not assigned a value under some condition, it is synthesized to hold its previous value. This is exactly the behavior of a register, and it automatically infers the q <= q feedback from the multiplexer model we saw earlier. This is the standard, concise way to model this behavior.

This single always block perfectly describes the N-bit register with enable and reset functionality we set out to build. A more verbose style, like the one using q_reg and q_next shown in the "Describing Registers in Verilog" video, is also valid but less common for a simple register. The single-block style is generally preferred for its clarity and conciseness.

4. Practice: Using Your New Module

You've designed a generic N-bit register. Now, let's use it.

Your task: Write the Verilog code to instantiate your Nbit_register module to create a 16-bit register.

• The instance name should be program_counter.
• Its clock input clk should connect to a wire named sys_clk.
• Its reset input should connect to sys_rst.
• Its enable input should connect to pc_write_en.
• Its data input d should connect to next_pc_value.
• Its output q should connect to current_pc.

// Wires that connect to our register instance
wire sys_clk;
wire sys_rst;
wire pc_write_en;
wire [15:0] next_pc_value;
wire [15:0] current_pc;

// Instantiation of the 16-bit register
Nbit_register #(
    .N(16)  // Overriding the default parameter N=32 with 16
) program_counter (
    .clk(sys_clk),
    .reset(sys_rst),
    .enable(pc_write_en),
    .d(next_pc_value),
    .q(current_pc)
);

Conclusion

Excellent work! You have now designed and implemented one of the most critical components in digital logic. You've combined your knowledge of sequential logic, assignment operators, and parameterization to create a robust and reusable building block.

Key Takeaways:

• A register is a group of flip-flops used to store a multi-bit value.
• A load enable signal provides crucial control, allowing the register to hold its value instead of loading new data on every clock cycle.
• This control is implemented in hardware using a multiplexer that selects between new data and the current stored value.
• In Verilog, this is modeled concisely using an if (enable) condition within an always @(posedge clk) block. If the condition is false, the register implicitly holds its value.
• The parameter keyword is used to create flexible and reusable modules, preventing code duplication and making designs easier to manage.

In our next lesson, we will build directly on what we've learned today. We will modify our register to create another essential component: a synchronous counter. You'll see that a counter is really just a register with some simple arithmetic logic added to its data path.