Parasitic Capacitance and Inductance in Power Switches

What Are Parasitics?

In the simplest terms, parasitics are the unintentional resistances, inductances, and capacitances that exist in a physical circuit. You don't add a "parasitic inductor" to your schematic, but the physical wire or trace you use to connect components has inductance all the same.

Let's start with a quick video that defines this concept clearly.

Where Do Parasitics Come From?

Parasitics aren't just random annoyances; they arise from fundamental physical principles and can be found in two main places: within the components themselves and in the PCB layout that connects them.

1. Parasitics within Components

No real-world component is pure. A capacitor isn't just a capacitor; it's a complex network of ideal and parasitic elements.

Switches (MOSFETs):
As the heart of a switching converter, the MOSFET is a major source of parasitics.

• Internal Capacitances: Due to its physical structure, a MOSFET has inherent capacitances:
  • $C_{gs}$ (Gate-Source): Must be charged to turn the device on.
  • $C_{ds}$ (Drain-Source): Also called output capacitance ($C_{oss}$). This capacitance must be charged and discharged every switching cycle, which is a major source of switching loss. We will focus heavily on this in the next module.
  • $C_{gd}$ (Gate-Drain): Also known as the "Miller capacitance." It couples the output back to the input and significantly affects switching speed.
• Package Inductances: The leads, pads, and internal bonding wires of the component package all have small but significant inductances. The inductance in the source connection, often called common source inductance, is particularly important because it is shared between the power path and the gate drive loop, which can slow down switching and increase losses.

Capacitors and Inductors:
Like MOSFETs, passive components also have parasitic elements.

2. Parasitics in the PCB Layout

The way you arrange components on a PCB is just as important as the components themselves. The traces, planes, and vias that connect everything create their own network of parasitic elements.

Parasitic Inductance and the Concept of Loop Area
Anytime current flows in a closed loop, that loop has inductance. The single most important principle for you to remember when reviewing a PCB layout is:

Inductance is proportional to the area of the current loop.

A large loop formed by a power trace and its ground return path will have high parasitic inductance. A small, tight loop will have low parasitic inductance. This is the foundation of high-frequency power layout.

The following video provides an excellent and intuitive demonstration of this principle.

Parasitic Capacitance
Any two conductive surfaces separated by an insulator (like the PCB's fiberglass material) form a capacitor. This can occur between:

• Two adjacent traces on the same layer.
• A trace on one layer and a ground or power plane on another layer.
• The large power and ground planes themselves.

Why Parasitics Matter: The "Hot Loop"

Now that we know what parasitics are and where they come from, why should we care?

In a switching converter, currents change extremely rapidly (high $dI/dt$). Because of the relationship $V=L\frac{dI}{dt}$, even a tiny parasitic inductance ($L$) can create large, damaging voltage spikes. These spikes cause electromagnetic interference (EMI) and stress components. Furthermore, the energy stored in these parasitic inductances and capacitances gets dissipated as heat (often in parasitic resistances), which reduces the converter's efficiency.

To manage this, designers focus on the "hot loop"—the part of the circuit with the fastest-switching currents. In a buck converter, this loop consists of the input capacitor, the top switch, and the bottom switch (or diode).

The energy stored in the parasitic inductance ($ESL$) of this hot loop causes voltage ringing, and this energy is then burned off as heat by the parasitic resistance ($ESR$), creating switching losses.

Practical Impact: Minimizing Parasitics Through Layout

Your goal is to review and optimize PCBs, and this is where these concepts become tools. A "good" layout is one that minimizes the area of the critical hot loops.

The DigiKey article provides a perfect case study comparing three different layouts for the same buck converter. By changing only the placement of the input capacitor, the parasitic inductance of the hot loop is dramatically altered, leading to measurable differences in efficiency and voltage ripple.

This case study demonstrates the core principle in action: placing critical components as close together as possible to minimize loop area reduces parasitic inductance, which in turn improves efficiency and reduces noise. This is a key pattern to look for during a PCB review.

+-------+      +----+      +----+
|       |------| Q1 |------| Q2 |
|  Cin  |      +----+      +----+
|       |-------------------------|
+-------+                         |
   |                              |
  GND ----------------------------+

+-------+   +----+
|       |---| Q1 |
|  Cin  |   +----+
|       |   +----+
+-------+---| Q2 |
   |        +----+
  GND

Conclusion

This lesson completes our tour of the fundamental building blocks of switching converters. We've moved from ideal components to the messy reality of parasitics.

Key Takeaways:

• Real-world components and PCB layouts contain parasitic resistance, inductance, and capacitance.
• Component Parasitics: Switches have internal capacitances ($C_{gs},C_{gd},C_{ds}$) and package inductance. Capacitors have ESR and ESL.
• Layout Parasitics: The most critical is loop inductance, which is proportional to the physical area enclosed by a current path.
• These parasitics are the primary cause of voltage spikes, ringing, EMI, and switching losses.
• A key goal of PCB layout for power converters is to minimize the area of high-current "hot loops" to reduce parasitic inductance.

Now that we understand what parasitics are and the problems they cause, we are ready to quantify their impact. In the next module, we will begin our investigation of The Hard Switching Problem. Our first lesson will explain exactly how the interplay of current, voltage, and these parasitic elements creates significant power loss during the switching transitions. This will lay the final piece of groundwork before we can truly appreciate the solution: Zero Voltage Switching.