Hello! Welcome back to our case study on PCB review.
In our last lesson, we focused on the most critical aspect of power converter layout: tracing and evaluating the high-current power loop and the high-speed gate drive loops. You learned that minimizing the inductance of these loops by reducing their physical area is the number one priority for ensuring stable operation and low noise.
Today, we'll build directly on that foundation. A good layout is more than just two well-managed loops. Many other subtle features can compromise your converter's performance, prevent Zero Voltage Switching from working correctly, or generate disruptive noise. Our goal for this lesson is to learn how to identify specific layout features that could compromise ZVS operation or introduce noise. We'll look at unintentional antennas, breaks in critical current paths, and how noise can "jump" from one part of the circuit to another.
1. The Switching Node: A High-Voltage Megaphone
In any switching converter, the point that connects the high-side switch, the low-side switch, and the output inductor is called the switching node (or SW node). This node's voltage swings rapidly between the input voltage and ground, giving it a very high rate of change of voltage, or .
A large copper area for the switching node acts like the plate of a capacitor. It can capacitively couple high-frequency noise currents into any nearby conductors, especially sensitive, high-impedance traces like analog feedback lines or even the gate drive circuit itself. This is a major source of instability and noise.
To see this in action and understand the main strategies for mitigation, let's return to the MIT lecture from our previous lesson.
Lecture 38: Gate Drive, Level Shift, Layout
This segment of "Lecture 38: Gate Drive, Level Shift, Layout" clearly explains how the switching node acts as a noise source and introduces the concept of shielding.
Please watch from 23:05 to 30:46. Focus on: The analogy of the switching node as one plate of a capacitor and a sensitive trace as the other. The three primary ways to reduce this capacitive coupling: reducing the node area, increasing the distance, and introducing a grounded Faraday shield between them.
As the video explains, there are two key layout rules for the switching node:
- Keep it small: The copper pour for the switching node should be just large enough to carry the required current. Any excess area is an unnecessary antenna that radiates noise.
- Keep it isolated: Maximize the distance between the switching node and any sensitive control or signal traces. If possible, place a ground plane between them to act as a shield.
2. Discontinuous Return Paths: The Detour That Creates a Loop
We established last time that high-frequency currents follow the path of least impedance, which means the return current tries to flow directly under or over the forward current path. This minimizes the loop area and thus the parasitic inductance.
A discontinuous ground plane is any feature that creates a slot, cut, or break in this ideal return path. When the return current encounters such a break, it is forced to detour, creating a much larger effective current loop.
Layout demonstrating BAD, BETTER, BEST and WORST case scenarios
This image from a Texas Instruments application note vividly illustrates the concept. The 'WORST' case shows a signal trace crossing a break in the ground plane. The return current (flowing on the ground plane) is forced to go all the way around the break, creating a massive loop that acts as a powerful antenna for EMI.
Common causes of discontinuous return paths include:
- Routing other signals: Cutting a slot in a ground plane to route a trace.
- Thermal cutouts: Creating a large void in a ground plane under a component for thermal isolation or to place thermal vias for a different component.
- Poor layer transitions: Using a via to move a signal to another layer but failing to provide a nearby "stitching" via for the ground return current.
The following resource provides a clear explanation and practical examples of these current paths.
Section 5 High Speed PCB Layout Techniques
This document, "Section 5 High Speed PCB Layout Techniques," clearly explains the importance of return current paths.
Please read pages 5-5 to 5-8. Focus on: Page 5-6: The 'WORST' and 'BAD' examples. See how the break in the ground plane and the long, winding trace create large loops. Page 5-7: The list of problems in the "High Frequency Output Current Path." Notice how placing bypass capacitors or source resistors far from the active device forces the current into a large, inductive loop.
A common real-world trade-off occurs with bottom-cooled surface-mount packages. To get heat out of the top switch in a half-bridge, you need a field of thermal vias under it. These vias connect to a thermal pad, but they must be electrically isolated from the ground return plane running on the layer below. This necessary cutout in the ground plane forces the return current to flow around it, increasing loop inductance.
Ground-plane clearance around a via field creates a lateral loop
This image from the Infineon application note we saw last lesson shows a real-world example. The red line is the forward current path through the transistors. The blue line is the return current path on the layer below. The cutout for the thermal vias of Q1 forces the return current to take a detour, creating a 'lateral loop' and significantly increasing inductance from an ideal 2.8 nH to 8.8 nH.
3. Vias: Not-So-Simple Connections
Vias are essential for multi-layer boards, but they are not ideal zero-impedance connections. A via has its own parasitic inductance and capacitance. For high-speed signals, this can be a problem, especially concerning the return current.
When a high-frequency signal trace passes through a via to another layer, its return current (on the ground plane) also needs to find a path to the corresponding ground plane on the new layer. If the nearest ground via is far away, the return path becomes a large loop.
The solution is to always place one or more ground vias immediately adjacent to the signal via.
Section 5 High Speed PCB Layout Techniques
Let's return to the TI layout guide to see a visual explanation of this problem and its solution.
Please read pages 5-15 and 5-16. Compare the two figures showing current density. Notice how the single return path via on page 5-15 results in a wide, dispersed current flow, while the multiple vias on page 5-16 keep the current flow tight and controlled, maintaining low impedance.
4. Noise Coupling into the Gate Drive
Now, let's tie these concepts together and see how they can compromise the sensitive gate drive circuit, which can directly prevent ZVS. The fast of the switching node and the high of the power loop can couple noise into the gate circuit through two main mechanisms:
- Capacitive Coupling: The switching node (high ) couples noise to the gate drive traces.
- Inductive Coupling: The magnetic field from the power loop (high ) induces a voltage in the gate drive loop.
If this injected noise is large enough, it can cause the gate voltage to ring, or even worse, cause a transistor that should be off to momentarily turn on, leading to shoot-through.
The following resource shows a powerful example of what happens when a gate drive circuit is laid out poorly, allowing for this kind of coupling.
Optimizing PCB layout for HV CoolGaN™ power transistors
The Infineon application note "Optimizing PCB layout for HV CoolGaN™ power transistors" has an excellent section illustrating these noise coupling issues.
Please read the section "Considerations for gate driver layout," focusing on Key concept #2 and the figures around it (25:00 - 29:30 in a spoken reading). Pay attention to: Figure 17: This shows the problematic parasitic capacitance from the high-side gate driver circuit down to the ground plane below. Figure 18: See the real-world effect of this capacitance—it creates instability and oscillation on the gate signal. Figure 19: This shows an even worse case where a combination of inductive and capacitive coupling causes sustained, destructive oscillation.
This brings us back to a key principle from our last lesson: placing a solid return plane directly under your gate drive circuit does two things simultaneously. It provides a tight vertical loop for minimum inductance, AND it acts as a shield, protecting the sensitive gate drive circuit from the noisy power stage below.
Test your understanding!
You are reviewing the PCB layout in Figure 19(a) from the Infineon note you just read. A colleague argues that the oscillation seen in 19(b) is only due to the large lateral power loop (red arrows).
Based on what you've learned, what other critical layout flaw is present in Figure 19(a) that also contributes to the oscillation?
Show answer
The colleague is only half right. The large lateral power loop creates a strong magnetic field (H-field) that inductively couples into the gate drive loop, which is one source of noise.
However, a second major flaw is the capacitive coupling from the high-side gate driver circuit (on the top layer) to the power loop's return path (the large brown plane on the second layer). As explained in Key Concept #2 and shown in Figure 17, this creates a parasitic capacitance between the gate circuit and an AC ground. The fast of the switching action injects current through this capacitance into the gate circuit, causing instability. The combination of both inductive and capacitive coupling is what leads to the severe, sustained oscillation.
Conclusion
In this lesson, we moved beyond the main power and gate loops to identify other critical layout features that can compromise a ZVS converter. Poor layout is often a story of unintended consequences, where parasitic elements create noise and instability.
Key Takeaways:
- The Switching Node is an Antenna: Keep the copper area of the high switching node as small as possible and keep it far from sensitive traces to minimize capacitive noise coupling.
- The Return Path is Non-Negotiable: High-frequency current wants to return directly under its forward path. Any break or slot in the ground/return plane forces the current into a large loop, increasing inductance and EMI.
- Mind Your Vias: Always provide adjacent ground "stitching" vias whenever a high-frequency signal trace changes layers to ensure a continuous, low-inductance return path.
- Shield Sensitive Circuits: Use ground planes to shield sensitive analog and gate drive circuits from the E-fields and H-fields generated by the noisy power stage. A dedicated ground plane under a circuit is the best way to do this.
In our next and final lesson of this case study module, we will shift our focus from the PCB layout to the components themselves. You'll learn how to look at a schematic and evaluate whether the chosen components (like MOSFETs and capacitors) are appropriate for the intended ZVS operating range.