Building a MUX with Logic Gates

What is a Multiplexer?

At its core, a multiplexer is a device that selects one of several input signals and forwards the selected input to a single output line. The choice of which input to select is controlled by a separate set of inputs known as select lines.

Think of it like a railroad switch that directs a train from one of several incoming tracks onto a single outbound track. The select lines are the lever that controls the position of the switch. This ability to choose a data source is fundamental for building a CPU, where you constantly need to decide, for example, whether to process data from memory, from a register, or from an external input.

For a formal introduction, the following article provides a great overview.

As the article mentions, the key relationship is that for $2^n$ data inputs, you need $n$ select lines. For our first design, we will start with the simplest case: a 2-to-1 Multiplexer, which has two data inputs and therefore requires just one select line.

Designing a 2-to-1 Multiplexer

Let's design a 2-to-1 MUX from first principles. Our goal is to create a circuit with two data inputs, which we'll call $I_0$ and $I_1$, one select line $S$, and one output $Y$. The behavior we want is:

• If $S=0$, the output $Y$ should be equal to the input $I_0$.
• If $S=1$, the output $Y$ should be equal to the input $I_1$.

1. The Boolean Expression

Knowing your background in Boolean math, we can translate this logic directly into an expression.

• The input $I_0$ is selected when $S=0$. In Boolean terms, the condition is $\bar{S}$. So, for this path to be active, we need the term $\bar{S}\cdot I_0$. If $\bar{S}$ is true (meaning $S=0$), the output is $I_0$.
• The input $I_1$ is selected when $S=1$. The condition is simply $S$. For this path to be active, we need the term $S\cdot I_1$.

Since the final output $Y$ should be either the result of the first case or the second case, we combine them with a logical OR operation. This gives us the complete Boolean expression for a 2-to-1 MUX:

2. The Logic Circuit

This expression is a direct recipe for the circuit diagram:

• We need a NOT gate to generate $\bar{S}$ from $S$.
• We need two AND gates to create the product terms $\bar{S}\cdot I_0$ and $S\cdot I_1$.
• We need one OR gate to combine the outputs of the AND gates.

The following video provides an excellent visual walkthrough of this exact design process.

The resulting circuit, along with its block diagram and truth table, is summarized perfectly in the top half of this image:

You may also recall from our lesson on universal gates that any logic function can be built with only NAND gates. The MUX is no exception. The circuit below shows an alternative, common implementation of a 2-to-1 MUX using four NAND gates.

Scaling the Design: The 4-to-1 Multiplexer

A computer needs to select between more than just two sources of data. The same principle we just used can be easily extended. To select from four inputs ($I_0,I_1,I_2,I_3$), we need two select lines ($S_1,S_0$). The binary value of these two select lines acts as an "address" to choose the input:

• $S_1{S}_0=00$ selects $I_0$.
• $S_1{S}_0=01$ selects $I_1$.
• $S_1{S}_0=10$ selects $I_2$.
• $S_1{S}_0=11$ selects $I_3$.

The Boolean expression expands accordingly:

This requires four 3-input AND gates and one 4-input OR gate. The lower half of the "2:1 and 4:1 Multiplexer" image you just saw shows this exact design. You can also see it explained in the next segment of the video you watched earlier.

The "Big Picture": Data Buses

Why is this so important for your goal of building a computer? Multiplexers are the key to creating a data bus. A bus is a set of wires that serves as a shared pathway for data between multiple components (like registers, the ALU, and memory). If multiple components try to send data on the same bus at the same time, their signals will conflict. A multiplexer solves this by ensuring only one component's data is placed on the bus at any given clock cycle.

The following video is a fantastic, practical demonstration of this exact problem. It's made in a simulator very similar to the ones you'll be using and directly addresses the challenge of moving data between registers.

Conclusion

In this lesson, you have designed one of the most versatile components in digital electronics. You've moved from single gates to a circuit that makes decisions and controls the flow of data.

Here are the main takeaways:

• A Multiplexer (MUX) acts as a digital switch, selecting one of its $2^n$ data inputs to route to a single output, based on the value of $n$ select lines.
• The logic for a MUX can be derived directly from its truth table into a Boolean expression in sum-of-products form.
• This Boolean expression provides a straightforward blueprint for implementing the MUX with AND, OR, and NOT gates.
• Multiplexers are the enabling technology for data buses, allowing multiple components within a computer to share a common communication pathway without conflict.

You now have a tool for selecting data. In the next lesson, we will explore its logical counterpart: the Demultiplexer (DMUX), a circuit that takes a single data input and routes it to one of several possible output lines. This is equally crucial for tasks like writing data to a specific register or memory location.