CMOS Active-Pixel Sensor Readout Architecture

Hello. Last lesson followed CCD charge packets through clocked registers to a shared output. A CMOS active-pixel sensor makes a different architectural choice: it converts the collected charge to a voltage at, or very near, its image location, then selects pixels electronically to place those voltages on column lines.

This lesson examines the circuit that makes that possible, from a three-transistor pixel to row addressing and column readout. We will then look at how adding a transfer gate changes the sensing node without changing the basic row-and-column architecture. Allow about 40 minutes, including the resources.

A voltage that can be read without moving the charge packet

Consider the three-transistor, or 3T, active pixel shown below. Its photodiode (PD) collects photoelectrons. The reset transistor, controlled by RG, establishes a starting voltage. The transistor labelled $M_{\mathrm{SF}}$ senses the photodiode voltage; SEL connects its output to the shared column line when that row is selected.

The photodiode’s junction capacitance, represented by $C_{\mathrm{PD}}$, is also its voltage-sensing node. Reset brings that node to a reference level $V_{\mathrm{R}}$. As $n$ electrons accumulate during exposure, its voltage falls approximately by

where $q$ is the elementary charge. This is the charge-to-voltage relation used at the CCD’s output last lesson, but its location has changed: each 3T pixel has its own sensing node. The approximation assumes that capacitance remains roughly constant over the voltage swing.

Why not connect that node directly to a long column wire? The wire and its attached circuitry present capacitance. Sharing charge with them would disturb the tiny stored signal. Instead, the photodiode voltage controls the gate of $M_{\mathrm{SF}}$, whose input draws very little current. With a bias-current load in the column circuitry, this transistor acts as a source follower: its output voltage follows changes at its gate while providing a better drive for the column line.

“Per-pixel amplification” therefore needs careful interpretation. The pixel contains an active transistor that buffers its signal; it does not necessarily multiply the voltage by a factor greater than one. A useful first-order description is $V_{\mathrm{col}}\simeq A{V}_{\mathrm{PD}}+b$, with follower gain $A$ generally below one and an offset $b$ set by operating conditions. The column sees an approximately $Anq/C_{\mathrm{PD}}$ change between the reset reference and the illuminated level.

Study the 3T schematic and commentary in these technical notes before moving to the array.

In the image’s timing plot, the PD trace rises on reset and falls while light-generated electrons accumulate. The marked integration intervals run between successive resets and readouts. The plot is an illustrative row sequence, not a claim that every row in the array begins exposure at once. Reading the voltage through a follower need not remove the photodiode’s stored charge; reset, rather than the act of voltage sensing, prepares this 3T pixel for another integration.

Selecting a row, then reading its columns

Pixels in one column share a long output line, but their source followers cannot all drive it at once. A row decoder activates SEL for one row, connecting that row’s pixel outputs to their respective column lines. Each column then carries one selected pixel’s voltage to circuitry at the edge of the array. Other rows remain disconnected.

The two coordinates play different electrical roles. Row addressing decides which pixels drive the columns. Column readout measures or stores the resulting voltages, after which a column multiplexer may send them to a shared output one at a time. Thus, “read one row” does not mean one pixel is sensed at a time: many columns can acquire the selected row in parallel, even if their stored results are subsequently serialized.

For an array with $R$ rows and $K$ columns, a simplified acquisition cycle is:

1. Select a row and allow its column voltages to settle.
2. Sample or convert the $K$ column signals, using column circuits operating in parallel where provided.
3. Select the next row and repeat.

The long column line has capacitance, so its voltage does not settle instantaneously when a new row is selected. Stronger drive or more bias current can shorten settling time, at a power cost. Column storage and multiplexing let an array share substantial measurement circuitry without requiring an entire output chain inside every pixel. The precise implementation varies: some designs serialize analogue samples, while others digitize signals in parallel at the columns.

This distinction is the central contrast with a CCD. In the CCD architecture studied last lesson, electrons from many image locations traverse registers before reaching a shared charge-to-voltage node. In a CMOS APS, pixel selection routes a voltage, not the image’s charge packets, along the column wiring. That avoids long-distance charge-transfer efficiency as a requirement of ordinary APS readout, though it introduces pixel-to-pixel transistor variation and a dense network of addressing and column circuits.

Row-by-row operation also has a timing consequence. If rows are reset and read at staggered times, their exposures occupy different intervals even when each interval has the same duration. A rapidly moving subject can therefore appear displaced from one row to another: rolling-shutter distortion. Electronic addressing makes readout flexible; it does not, by itself, make exposure simultaneous.

A transfer gate separates collection from sensing

The 3T design uses the photodiode both to collect electrons and to convert their count into a voltage. A common alternative places a transfer gate between the photodiode and a small floating-diffusion (FD) sensing node. Electrons integrate in the photodiode; during readout, the gate transfers them to FD. A reset transistor sets FD’s reference voltage, and the in-pixel source follower and row-select transistor deliver its voltage to a column line.

Watch this explanation of the four-transistor arrangement. Keep the extra transfer gate in view: it is the key difference from the 3T schematic, while the follower and row-select roles remain recognizable.

The photodiode-to-FD transfer is local. It does not turn the entire CMOS array into the vertical and horizontal charge-transfer registers of a CCD. Separating collection from sensing also lets the FD capacitance be chosen differently from the photodiode’s collection capacitance. If $C_{\mathrm{FD}}$ is small, a transferred packet produces a larger voltage change, approximately $nq/C_{\mathrm{FD}}$. The engineering constraints are then whether charge transfers completely and whether the resulting voltage remains within the readout circuit’s usable range.

An early peer-reviewed active-pixel design by S. Mendis, S. Kemeny, and E. Fossum makes the sequence especially concrete. Its detector is a photogate rather than the photodiode in our 3T drawing. The important architectural point is the same: collected charge is transferred to a nearby FD node, and that node’s voltage is read through a pixel source follower onto a column line.

The paper’s column capacitors hold a reset reference and a post-transfer signal. Subtracting those measurements is correlated double sampling: noise present in both closely spaced measurements, including the FD’s reset uncertainty under suitable conditions, can largely cancel. The cancellation is not universal; noise introduced independently during sampling, or changes between the two measurements, remains.

There is a subtle 3T distinction. In a simple sequence that reads a signal and then samples the following reset, that reset is not necessarily the one that established the signal’s starting voltage before exposure. Subtraction can remove offsets, but it does not automatically cancel the earlier reset uncertainty. A separate pre-exposure reset sample could in principle be retained, although the long interval makes drift and storage more demanding. With a transfer-gate pixel, the reset level can be sampled immediately before moving the stored photodiode charge onto FD, so the two FD measurements share a much closer reference.

This addition of circuitry has an optical cost: devices and wiring compete for pixel area with the light-collecting region. Engineering the photodiode, transistor layout, and shared circuitry is therefore part of sensor evolution, not merely an implementation detail. We will return to the resulting noise and saturation trade-offs in the next lesson.

Conclusion

A CMOS active pixel measures charge locally and uses an in-pixel source follower to buffer the resulting voltage. A row-select transistor connects the chosen row to shared column lines; column circuits then sample, multiplex, or digitize those signals. The 3T pixel converts charge on its photodiode capacitance, while a transfer-gate design moves charge a short distance to a separate sensing node. Neither requires the image-wide charge transport that defined last lesson’s CCD.

Next, we will use these sensing and sampling points to separate photon shot noise, read noise, and fixed-pattern noise in a photon-transfer analysis, then relate their limits to dynamic range.