MOSFETs as Voltage-Controlled Switches

Hello! Welcome back to our crash course on computational structures.

In our last few lessons, we've treated logic gates as abstract "black boxes" defined by their Voltage Transfer Characteristics (VTCs) and noise margins. Today, we're going to open up that box and look at the fundamental components inside.

Our goal is to describe the operation of N-channel and P-channel MOSFETs as voltage-controlled switches. These tiny transistors are the building blocks of virtually all modern digital electronics. Understanding how they work as simple switches is the first and most crucial step toward understanding how complex circuits like processors are built.

1. From Logic to Transistors

In digital circuits, we need a way to physically implement Boolean logic (AND, OR, NOT). The device that allows us to do this is the transistor, specifically the Metal-Oxide-Semiconductor Field-Effect Transistor, or MOSFET.

As an Electronics and Electrical Engineering student, you've likely encountered transistors in analog contexts, where they act as amplifiers. For digital design, we'll use a much simpler model: the transistor as a perfect, electrically controlled switch.

A MOSFET has three main terminals:

Gate (G): The control input. The voltage applied here determines if the switch is ON or OFF.
Source (S): One end of the switch.
Drain (D): The other end of the switch.

Current flows between the source and drain, but this flow is controlled by the voltage at the gate. There are two "flavors" of MOSFETs that we use together: the N-channel MOSFET (nMOS) and the P-channel MOSFET (pMOS).

2. The Basic Switch Model

Let's start with a short video that introduces both transistor types and their fundamental behavior as complementary switches.

Building logic gates from MOSFET transistors

This video from EngMicroLectures provides a great overview of how nMOS and pMOS transistors function as electrically controlled switches. It shows their symbols and explains their opposite, or 'complementary,' behavior.

Watch the first 3 minutes (from 0:00 to 3:04). Focus on how a '1' (high voltage) at the gate affects the nMOS and pMOS differently, and vice versa for a '0' (low voltage).

As the video showed, nMOS and pMOS transistors have opposite behaviors, which is why they are called complementary. This is the 'C' in CMOS (Complementary Metal-Oxide-Semiconductor), the dominant technology for building digital chips.

Let's break down each type.

N-Channel MOSFET (nMOS)

The nMOS transistor can be thought of as a normally-open switch that closes when you apply a high voltage to its gate.

Gate = LOW (Logic '0'): The switch is OFF (an open circuit). No current can flow between source and drain.
Gate = HIGH (Logic '1'): The switch is ON (a closed circuit). Current can flow freely between source and drain.

Technically, the nMOS transistor turns on when its gate-to-source voltage ( $V_{GS}$ ) exceeds a certain threshold voltage ( $V_{t h}$ ) . In digital logic, we simplify this to 'HIGH' voltage turns it on.

NMOS Transistor as a Voltage-Controlled Switch — This diagram illustrates the switch model for an nMOS transistor. A gate voltage $V_{GS}$ greater than the threshold voltage $V_T$ turns the switch ON, creating a path between the drain and source.

Because an nMOS transistor turns on with a high input, it is excellent for connecting a node to the low voltage rail, Ground (GND). We call this a pull-down network.

P-Channel MOSFET (pMOS)

The pMOS transistor works in the opposite way. You can think of it as a normally-open switch that closes when you apply a low voltage. Note the bubble on the gate symbol, which signifies this inverted behavior.

Gate = LOW (Logic '0'): The switch is ON (a closed circuit).
Gate = HIGH (Logic '1'): The switch is OFF (an open circuit).

Because a pMOS transistor turns on with a low input, it is excellent for connecting a node to the high voltage rail, Vdd (power supply). We call this a pull-up network.

3. "Strong" vs. "Weak" Logic Levels

While we can model MOSFETs as perfect switches, there's a crucial subtlety. They are not equally good at passing both logic '0' and logic '1'.

An nMOS transistor passes a "strong 0" but a "weak 1". This means it can pull a node's voltage all the way down to GND, but it struggles to pull a node all the way up to Vdd.
A pMOS transistor passes a "strong 1" but a "weak 0". It can pull a node's voltage all the way up to Vdd, but it struggles to pull a node down to GND.

This behavior is why we use nMOS for pull-down networks (connecting to '0') and pMOS for pull-up networks (connecting to '1'). The following video explains the physics behind this in more detail.

CMOS Logic Gates Explained | Logic Gate Implementation using CMOS logic

Now that we know the basic on/off behavior, let's look at a crucial detail: how well each type of transistor passes logic '1' and logic '0'. This video from ALL ABOUT ELECTRONICS explains why nMOS transistors are good at pulling a voltage down to '0' (strong 0) but not so good at pulling it up to '1' (weak 1), and the reverse for pMOS transistors.

Watch from 7:01 to 11:46. The first part (7:01-9:17) explains why nMOS passes a 'weak 1'. The second part (9:17-11:46) explains why pMOS passes a 'weak 0'. Understanding this is fundamental to why CMOS circuits are constructed the way they are.

4. Summary

Let's consolidate everything into a single table. This is the core knowledge you need to take away from this lesson.

Feature	n-channel MOSFET (nMOS)	p-channel MOSFET (pMOS)
Symbol	No bubble on gate	Bubble on gate
Control Input	Gate voltage	Gate voltage
Turns ON when...	Gate is HIGH (Logic '1')	Gate is LOW (Logic '0')
Turns OFF when...	Gate is LOW (Logic '0')	Gate is HIGH (Logic '1')
Best Use	Pull-down network (connects output to GND)	Pull-up network (connects output to Vdd)
Passes well...	Strong '0'	Strong '1'
Passes poorly...	Weak '1'	Weak '0'

For a final reinforcement, you can review the following slide from a Stanford University lecture, which neatly summarizes the complementary action of nMOS and pMOS devices.

[PDF] 8. MOS Transistors, CMOS Logic Circuits

These lecture slides from Stanford University provide a very concise summary of the complementary nature of nMOS and pMOS devices.

Please review slide 11, titled 'nMOS and pMOS Devices “Complement” Each Other'. It cleanly summarizes the on/off conditions for both transistor types and their typical connections to the power supply (Vdd) and Ground (Gnd).

Conclusion

In this lesson, we peeled back a layer of abstraction to see the fundamental switches that power our digital world.

Key Takeaways:

MOSFETs are the building blocks of digital logic, acting as voltage-controlled switches.
An nMOS transistor turns ON with a HIGH gate voltage. It's used in pull-down networks to connect outputs to Ground, passing a "strong 0".
A pMOS transistor turns ON with a LOW gate voltage. It's used in pull-up networks to connect outputs to Vdd, passing a "strong 1".
Their opposite behaviors make them complementary, forming the basis of CMOS technology.

Preview of the Next Lesson

Now that we have our two types of switches, a pull-up switch (pMOS) and a pull-down switch (nMOS), how can we combine them to create a logic gate? In the next lesson, we will construct a CMOS inverter and trace its VTC. This will directly connect the transistor behavior we learned today to the VTCs and logic levels we studied in previous lessons, completing the link from physical transistors to the digital abstraction.

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