Parallel Primitives in CUDA

Implement a naive parallel reduction and analyze its inefficiencies from divergence and non-coalesced access.

Optimize a parallel reduction by using sequential addressing and shared memory to improve performance.

Further optimize the reduction using warp shuffle instructions for efficient intra-warp communication.

Implement a parallel histogram kernel using atomic operations to handle contention.

Implement the up-sweep (reduction) phase of the Blelloch scan algorithm within a single thread block.

Implement the down-sweep phase to complete a single-block exclusive scan algorithm.

Implement gather and scatter parallel data movement patterns in CUDA kernels.