Creating a Basic Testbench

1. What is a Testbench?

Before writing any code, it's vital to understand the role of a testbench. A design module (like a multiplexer or an adder) describes hardware that can be synthesized and physically built into a chip. A testbench, on the other hand, is written only for simulation. It contains code that generates inputs and checks outputs, but it is never synthesized into hardware.

The testbench acts as a wrapper around your Design Under Test (DUT).

The core components of a simple testbench are:

1. A Module Declaration: A testbench is a Verilog module, but it has no input or output ports. It is entirely self-contained.
2. Signal Declarations:
   • Inputs to the DUT are declared as reg type in the testbench. This is because we will be assigning values to them within a procedural block.
   • Outputs from the DUT are declared as wire type in the testbench, as they are being driven by the DUT.
3. DUT Instantiation: You instantiate your design module within the testbench, just as you learned in the previous lesson. You'll use named port mapping to connect the reg and wire signals you just declared to the DUT's ports.
4. Stimulus Generation: You provide a sequence of input values to the DUT to test its logic under different conditions.

2. Generating Stimulus: initial Blocks and Delays

To apply a sequence of inputs, we need two new Verilog constructs: the initial block and the delay operator (#).

As you read, here's a summary of the key ideas:

• initial Block: This is a procedural block that starts executing at time 0 of the simulation and runs through its statements sequentially, only once. This makes it perfect for defining a fixed test sequence.

  initial begin
    // Stimulus commands go here
  end
  

• timescale and Delays (#): Simulation in Verilog happens in a simulated time. The `timescale directive, placed at the top of a file, defines the units of this time. For example, `timescale 1ns / 1ps means that delays are measured in nanoseconds (1ns) with a precision of picoseconds (1ps).
  • The # operator creates a delay. #10; pauses the execution of the block for 10 time units. We use this to hold a set of input values steady for a period before changing them to the next test vector.

The image below shows a perfect example of an initial block applying a sequence of stimulus vectors to test a 3-input design. Notice how each set of inputs is followed by a #10 delay to allow time for the simulation to process the change.

3. A Complete Testbench Example: Half Adder

Now, let's walk through creating a testbench for a simple half adder. This practical example will bring all the concepts together.

First, here is the Verilog module for our DUT, the half_adder:

// Design Under Test (DUT)
module half_adder (
    input  a,
    input  b,
    output sum,
    output carry
);
    assign {carry, sum} = a + b;
endmodule

Next, we will build a testbench to verify this half_adder. The following video provides an excellent step-by-step guide. We will focus on the testbench creation, instantiation, and stimulus generation.

Based on the video, the complete testbench code looks like this:

`timescale 1ns / 1ps

// Testbench Module (no ports)
module half_adder_tb;

    // 1. Declare signals to connect to DUT
    // Inputs to DUT are 'reg'
    reg  a;
    reg  b;
    // Outputs from DUT are 'wire'
    wire sum;
    wire carry;

    // 2. Instantiate the Design Under Test (DUT)
    half_adder dut (
        .a      (a),
        .b      (b),
        .sum    (sum),
        .carry  (carry)
    );

    // 3. Apply stimulus
    initial begin
        // Test case 1: a=0, b=0
        a = 1'b0;
        b = 1'b0;



        #10; // Wait 10 ns

        // Test case 2: a=0, b=1
        a = 1'b0;
        b = 1'b1;



        #10; // Wait 10 ns

        // Test case 3: a=1, b=0
        a = 1'b1;
        b = 1'b0;



        #10; // Wait 10 ns

        // Test case 4: a=1, b=1
        a = 1'b1;
        b = 1'b1;



        #10; // Wait 10 ns
    end
    
    // 4. Observe the results (we'll study this more later)
    initial begin
        $monitor("Time=%0t ns, a=%b, b=%b, sum=%b, carry=%b",
                 $time, a, b, sum, carry);
    end

endmodule

When you run this simulation, the $monitor task would produce an output like this, allowing you to verify that for each input (a, b), the sum and carry are correct:

Time=0 ns, a=0, b=0, sum=0, carry=0
Time=10 ns, a=0, b=1, sum=1, carry=0
Time=20 ns, a=1, b=0, sum=1, carry=0
Time=30 ns, a=1, b=1, sum=0, carry=1

Conclusion

In this lesson, you've learned how to create a fundamental piece of the verification puzzle: the testbench. By writing code that exists only to test your hardware design, you can gain confidence that your logic is correct before moving on to more complex stages of the design flow.

Here are the key takeaways:

• A testbench is a non-synthesizable Verilog module used to simulate and verify a Design Under Test (DUT).
• The testbench module has no ports. It drives the DUT's inputs with reg variables and reads its outputs with wire variables.
• The initial block is used to define a sequence of stimulus commands that runs once at the start of the simulation.
• The delay operator (#) is essential for controlling time and separating different input stimulus vectors.

In our next lesson, we'll expand on this foundation. You'll learn how to generate a periodic clock signal, a requirement for testing sequential circuits, and we will take a much deeper look at using system tasks like $display and $monitor to create more sophisticated testbenches.