Computer Systems Architecture

Explain the difference between combinational and sequential circuits, focusing on the concept of 'state'.

Distinguish between synchronous and asynchronous sequential circuits, and describe a clock signal's properties (period, frequency, active edge).

Analyze the behavior of an SR latch built from cross-coupled NOR gates and derive its characteristic table.

Analyze the behavior of an S'R' latch built from cross-coupled NAND gates and identify the forbidden input condition.

Describe the operation of a gated (level-sensitive) SR latch and the role of the enable input.

Construct a gated D latch and explain how it eliminates the invalid input state of the SR latch.

Identify timing issues in level-sensitive latches, such as transparency.

Explain edge-triggering using a master-slave configuration as an example.

Derive and explain the characteristic table, characteristic equation, and excitation table for the D flip-flop.

Derive and explain the characteristic table, characteristic equation, and excitation table for the JK flip-flop.

Derive and explain the characteristic table, characteristic equation, and excitation table for the T flip-flop.

Convert one type of flip-flop into another (e.g., JK to D, D to T) using combinational logic.

Describe the function of asynchronous preset and clear inputs on a flip-flop.

Interpret setup time, hold time, and propagation delay from a flip-flop timing diagram.

Identify state variables, inputs, and outputs in a given synchronous sequential circuit.

Derive the next-state and output equations from a circuit diagram.

Construct the state table and state diagram of a synchronous sequential circuit from its equations.

Distinguish Mealy and Moore machines based on their circuit diagrams and state tables.

Produce a timing diagram for a sequential circuit given input waveforms and an initial state.

Translate a word-problem specification into a state diagram for a Mealy or Moore FSM.

Reduce the number of states in a state table by identifying and merging equivalent states.

Assign binary codes to states and justify the choice (e.g., sequential, Gray, one-hot).

Derive the next-state and output equations from a state-assigned table using K-maps.

Implement an FSM using D flip-flops and combinational logic from its equations.

Implement an FSM using JK or T flip-flops via their excitation tables.

Case study: Design a Mealy '1011' sequence detector from specification to a final circuit using D flip-flops.

Case study: Design a Moore '1011' sequence detector from specification to a final circuit using JK flip-flops.

Construct an n-bit parallel-load register from D flip-flops with a load-enable control.

Describe the operation of a basic shift register and its serial-in/serial-out behavior.

Apply shift registers to serial-to-parallel and parallel-to-serial data conversion.

Design the single bit-slice of a universal shift register using a multiplexer to select its mode of operation.

Cascade bit-slices to build a complete 4-bit universal shift register with mode-select control.

Explain the operation and propagation-delay limitations of asynchronous (ripple) counters.

Design a synchronous binary up-counter of a given bit width using T or JK flip-flops.

Design a synchronous up/down counter controlled by a direction input.

Design a synchronous counter with an arbitrary modulus (e.g., mod-6, mod-10) using the FSM design method.

Use a counter with parallel load to implement a custom counting sequence.

Analyze a complex, exam-style synchronous sequential circuit by deriving its state table, state diagram, and timing diagram.

Execute a full FSM design process for a complex word problem (Mealy machine), from state diagram creation and minimization to final circuit implementation.

Execute a full FSM design process for a complex word problem (Moore machine), from state diagram creation and minimization to final circuit implementation.

Design and implement a synchronous counter with a non-standard sequence or modulus, deriving the minimal logic using a specified flip-flop type.