Optimizing ZVS Converter Parameters

1. Dead-Time Optimization: The Critical Timing Window

In ZVS topologies that use a half-bridge or full-bridge structure, dead-time is the brief period when both the high-side and low-side MOSFETs in a leg are commanded to be off. This is done to prevent "shoot-through," a catastrophic condition where both switches conduct simultaneously, shorting the power supply.

In ZVS converters, this dead-time is not just a safety measure; it is an active and critical part of the switching cycle. It is the window of opportunity for the inductor current to discharge the MOSFET's output capacitance ($C_{oss}$) and achieve ZVS. Getting this timing right is a classic engineering trade-off.

• If the dead-time is too short: The $C_{oss}$ won't have time to fully discharge before the MOSFET turns on. This results in a partial or complete loss of ZVS, reintroducing the hard-switching losses we tried to eliminate. In the worst case, it can lead to shoot-through.
• If the dead-time is too long: After the $C_{oss}$ is discharged, the inductor current has nowhere to go but through the MOSFET's body diode. This causes two problems:
  1. Body Diode Conduction Loss: You incur losses equal to $P=V_F\times I_{diode}\times t_{conduction}$.
  2. Reverse Recovery ($Q_{rr}$) Loss: For silicon MOSFETs, longer body diode conduction builds up more stored charge ($Q_{rr}$), leading to a larger and more destructive current spike when the opposing switch turns on.

There is an optimal dead-time that is just long enough to ensure ZVS but no longer.

Calculating the Optimal Dead-Time

While the optimal dead-time is often fine-tuned empirically on the bench, a very good initial estimate can be calculated from datasheet parameters. This is a crucial first step in a design review.

A fantastic resource for this is the application note "Optimum Dead Time Selection in ZVS Topologies" from Vishay. It provides a clear methodology for calculating the required dead-time.

As the paper shows, the total required dead-time ($T_{dt}$) is the sum of several intervals related to turning the old MOSFET off and discharging the new MOSFET's capacitance:

$T_{dt}\ge T_{LSH}+T_{GSP}+T_{GPT}+T_{DSD}$

Where:

• $T_{LSH}$ is the driver's level-shift delay.
• $T_{GSP}$ and $T_{GPT}$ are delays related to discharging the gate of the outgoing MOSFET through its various capacitance regions.
• $T_{DSD}$ is the time it takes the inductor current to resonantly discharge the parasitic capacitance on the switching node.

This calculation shows how the parameters from our last lesson ($C_{iss0}$, $Q_{sw}$, $C_{oss}$) directly feed into the optimization of circuit timing.

The $Q_{rr}$ Penalty

The Vishay paper highlights the penalty of excess dead-time from body diode conduction. For silicon MOSFETs, this is made far worse by reverse recovery. Let's revisit the video from EPC to see a powerful illustration of this.

This demonstrates a key optimization strategy: for silicon MOSFET-based ZVS converters, minimizing dead-time to the calculated optimum is critical for efficiency and reliability. Simply adding a large "safety margin" is counterproductive.

Advanced Strategy: Adaptive Dead-Time Control

Manually setting a fixed dead-time is a compromise, as the optimal value can change with operating conditions. High-end controllers implement an adaptive dead-time (or "shoot-through protection") scheme.

This strategy involves circuitry that monitors the voltage on the switching node. It inhibits the turn-on of a MOSFET until it senses that the node voltage has fallen all the way (indicating body diode conduction has begun). This automatically ensures ZVS while minimizing body diode conduction time.

2. Resonant Parameter Optimization

The second pillar of ZVS optimization is tuning the resonant components. In ZVS converters, the primary inductor current is used to charge and discharge the MOSFET parasitic capacitances. The "resonant parameters"—such as the resonant inductor in a ZVS Phase-Shifted Full-Bridge or the magnetizing inductance in an Active Clamp Flyback—determine how much energy is available for this transition.

The Core Trade-Off: ZVS Range vs. Light-Load Efficiency

This is one of the most fundamental trade-offs in ZVS design.

• To achieve ZVS, the energy stored in the resonant inductance ($\frac{1}{2}L{I}^2$) during the dead-time must be greater than the energy stored in the MOSFET's output capacitance ($E_{oss}$).
• Strategy 1: Prioritize Wide ZVS Range. By using a smaller inductance value, the current ($I$) ramps up to a higher level. This provides ample energy to overcome $E_{oss}$ even when the main load current is very low. The benefit is robust ZVS operation across a wide load range. The drawback is that this large current is "circulating" in the primary circuit, not being delivered to the load, which causes significant conduction losses ($I^{2}R$) and hurts light-load efficiency.
• Strategy 2: Prioritize Light-Load Efficiency. By using a larger inductance value, the circulating current is kept low. This dramatically improves efficiency at light loads. The drawback is that at some point, the energy in the inductor will be insufficient to fully discharge the MOSFET capacitance, and ZVS will be lost.

A practical design must balance these competing goals based on the application's requirements (e.g., meeting efficiency standards at 10% load).

Case Study: Optimizing an Active Clamp Flyback

The Active Clamp Flyback (ACF) is a perfect topology to study this trade-off. It relies on the transformer's magnetizing current to achieve ZVS. Specifically, it needs a negative "valley" current to pull the switch node voltage down to zero.

As the paper demonstrates, the optimization process is:

1. Determine the Energy Needed: Calculate the total parasitic capacitance on the switching node ($C_{lump}$).
2. Calculate Required Current: Based on $C_{lump}$ and the available dead-time, calculate the minimum magnetizing current valley ($I_{valley}$) needed to discharge it.
3. Select the Resonant Parameter: Choose the magnetizing inductance ($L_{mag}$) that will produce this required $I_{valley}$ under the worst-case operating conditions (e.g., minimum input voltage, full load).

Advanced Strategy: Variable Frequency & Multi-Mode Operation

A fixed inductance value is always a compromise. A more advanced strategy, as hinted at in the onsemi paper, is to dynamically change the converter's operating point. By increasing the switching frequency at light loads, the controller can reduce the magnetizing current swing. This effectively reduces the amount of circulating energy to the minimum required for ZVS, dramatically boosting light-load efficiency.

Many modern controllers take this even further, implementing multi-mode operation. They might operate as a ZVS converter at high loads, then transition to a different mode (like Discontinuous Conduction Mode or skip-cycle mode) at very light loads where ZVS is no longer efficient or necessary. As a reviewer, seeing these features implemented in a controller IC is a sign of a sophisticated, highly-optimized design.

Conclusion

You can now see that optimizing a ZVS converter goes far beyond just picking good parts. It involves a delicate and deliberate tuning of the operating parameters to balance competing objectives.

Key Takeaways:

• Dead-time optimization is a crucial trade-off. The goal is a time window just long enough to achieve ZVS but short enough to minimize body diode conduction and reverse recovery losses. The optimal value can be calculated from datasheet parameters.
• Resonant parameter optimization is a trade-off between maintaining ZVS over a wide load range (requiring more circulating energy) and achieving high efficiency at light loads (requiring less circulating energy).
• Advanced optimization strategies like adaptive dead-time control, variable frequency operation, and multi-mode control are used in modern converters to dynamically adjust these trade-offs and maximize efficiency across all operating conditions.

In our next lesson, we will complete our analysis of efficiency by examining the primary loss mechanisms that persist even in an optimized ZVS converter, such as conduction losses, gate drive losses, and magnetic core losses.