Minimizing Losses in Hard-Switched Designs

Hello!

In our last few lessons, we've explored the two major drawbacks of hard switching: power dissipation from V-I overlap and the generation of electromagnetic interference (EMI) from fast switching edges. We've defined the problem and even calculated the energy lost in a single switching transition.

Now, we'll connect everything to the real-world parameters you control or observe in a power converter. Your learning goal for this lesson is to identify how switching frequency, voltage, and current affect losses in hard-switched designs.

Understanding these relationships is the key to analyzing trade-offs in any power supply design. It's the "why" behind component choices and operating points you'll see when reviewing schematics and PCBs. This lesson provides the final piece of motivation for why engineers go to great lengths to implement soft-switching techniques like ZVS.

The Major Loss Components in a MOSFET

When a MOSFET is used as a switch, its total power dissipation is primarily the sum of three distinct types of losses:

Conduction Loss ( $P_{co n d}$ ): The resistive heating that occurs when the MOSFET is fully ON and conducting current. This is a static loss, happening during the on-state.
Switching Loss ( $P_{s w}$ ): The loss that occurs during the turn-on and turn-off transitions, caused by the temporary overlap of significant voltage and current. This is a dynamic loss.
Gate Drive Loss ( $P_{g a t e}$ ): The power required to charge and discharge the MOSFET's gate capacitance to turn it on and off. This is also a dynamic loss.

Our goal is to understand how the main operating parameters—bus voltage ( $V_{b u s}$ ), load current ( $I_{l o a d}$ ), and switching frequency ( $f_{s w}$ )—influence each of these.

Conduction vs. Switching Loss: A Visual Deep Dive

Let's start by looking at conduction and switching losses, which are typically the two largest contributors. The following video provides an excellent breakdown.

Lecture 15: Switching Losses and Snubbers

This lecture from MIT OpenCourseWare walks through the calculation of both conduction and switching losses in a buck converter, clearly illustrating how they are derived.

Please watch the following segments: Conduction Loss (2:49 - 6:34): Pay attention to the formula. Notice that it is fundamentally an I^2R loss, depending on the RMS current and the MOSFET's on-state resistance (R_{ds(on)}). Switching Loss (6:34 - 13:03): Focus on the waveforms and the final formula. Observe how voltage (V), current (I), transition times (t), and switching frequency (f) all contribute to the final power loss calculation.

Let's summarize the key dependencies based on the video:

Conduction Loss ( $P_{co n d}$ )

As the video explained, conduction loss is fundamentally resistive heating.

P_{co n d} = I_{R M S}^{2} \times R_{d s (o n)}

Impact of Current ( $I_{l o a d}$ ): This is the most significant factor. Since $I_{R M S}$ is directly related to the load current, conduction loss scales with the square of the current. Doubling the load current quadruples the conduction loss.
Impact of Voltage ( $V_{b u s}$ ): No direct impact.
Impact of Frequency ( $f_{s w}$ ): No direct impact. This loss occurs during the on-state, not during the transition.

Switching Loss ( $P_{s w}$ )

Switching loss is the energy lost per transition, multiplied by the number of transitions per second.

P_{s w} \approx \frac{1}{2} V_{b u s} \times I_{l o a d} \times (t_{r} + t_{f}) \times f_{s w}

Where $t_{r}$ and $t_{f}$ are the rise and fall times of the switch.

Impact of Current ( $I_{l o a d}$ ): The loss is linearly proportional to the load current. Higher current means more power is dissipated during the overlap.
Impact of Voltage ( $V_{b u s}$ ): The loss is linearly proportional to the bus voltage. Switching a higher voltage is inherently more lossy.
Impact of Frequency ( $f_{s w}$ ): The loss is linearly proportional to the switching frequency. Each cycle has two transitions (on and off), so switching twice as often means you incur this loss twice as many times per second.

Bringing It All Together: A Comprehensive View

Conduction and switching losses are just part of the story. Gate drive loss and other secondary losses also depend on these parameters. The following reading provides a fantastic, practical summary of how each parameter affects overall performance.

MOSFET Power Loss Calculator

This guide from DMCinfo, 'MOSFET Power Loss Calculator and Guide for Engineers,' gives a clear, parameter-by-parameter breakdown of the effects on performance and loss. It's a great reference.

Please read the section 'Electrical Parameters.' For each parameter (Vbus, Current, f_sw), focus on the 'How it affects performance' and 'Design implications' descriptions. This directly answers our main question for today.

Now let's use a technical application note from Texas Instruments to formalize these ideas and introduce Gate Drive Loss.

MOSFET power losses and how they affect power-supply ...

This application note, 'MOSFET power losses and how they affect power-supply efficiency,' provides the concise formulas and trade-off discussions common in component datasheets and engineering documents.

Read through the document from the beginning up to the end of the 'Gate-drive losses' section (before 'Figure 8'). Focus on: Equation 3 (Conduction Loss): Confirming its dependence on current and R_{DS(on)}. Equation 4 (Switching Loss): Seeing the relationship with V_{IN}, I_{OUT}, and f_{SW}. Equation 5 (Gate Loss): Noting its dependence on gate charge (Q_G), gate voltage (V_G), and switching frequency (f_{SW}).

Gate Drive Loss ( $P_{g a t e}$ )

From the TI document, we get the formula for gate drive loss:

P_{g a t e} = Q_{G (T O T)} \times V_{G} \times f_{s w}

Impact of Current ( $I_{l o a d}$ ) & Voltage ( $V_{b u s}$ ): No direct impact. However, MOSFETs chosen for higher voltage/current applications often have a larger silicon die, which leads to a higher total gate charge ( $Q_{G}$ ), indirectly increasing this loss.
Impact of Frequency ( $f_{s w}$ ): The loss is linearly proportional to the switching frequency. Just like with switching loss, charging and discharging the gate more often consumes more power.

The Designer's Dilemma: Frequency vs. Efficiency

We can now summarize the dependencies in a table.

Loss Component	Proportionality to Load Current ( $I_{l o a d}$ )	Proportionality to Bus Voltage ( $V_{b u s}$ )	Proportionality to Switching Freq. ( $f_{s w}$ )
Conduction Loss	$\propto I_{l o a d}^{2}$	None	None
Switching Loss	$\propto I_{l o a d}$	$\propto V_{b u s}$	$\propto f_{s w}$
Gate Drive Loss	None	Indirect	$\propto f_{s w}$

This table reveals the fundamental trade-off in hard-switched converter design. Engineers want to increase switching frequency to use smaller (and cheaper) inductors and capacitors, which increases power density. However, doing so directly increases both switching and gate drive losses.

At low frequencies, the total loss is dominated by $I^{2} R$ conduction loss. As frequency increases, the two frequency-dependent loss terms begin to grow and eventually overtake the conduction loss.

This graph from the Texas Instruments application note perfectly illustrates the trade-off. At low frequencies, conduction loss (blue line) dominates. As frequency increases, switching loss (red line) and gate loss (green line) rise linearly and become the main sources of inefficiency.

Test your understanding!

You are reviewing a 48V DC-DC converter design. The lead engineer proposes doubling the switching frequency from 200 kHz to 400 kHz to reduce the size of the main magnetic components. Based on the relationships we've discussed, what are the two primary negative consequences for the power MOSFET's efficiency that you should immediately anticipate?

Show answer

By doubling the switching frequency, you should anticipate that:

Switching Loss ( $P_{s w}$ ) will approximately double. Since $P_{s w} \propto f_{s w}$ , this is a direct consequence.
Gate Drive Loss ( $P_{g a t e}$ ) will also approximately double. This is because $P_{g a t e} \propto f_{s w}$ .

The conduction loss will remain largely unchanged. The overall effect will be a significant increase in the total power dissipated by the MOSFET, leading to lower efficiency and a hotter device.

Conclusion

In this lesson, we've formalized the relationship between the key operating parameters of a converter and its primary loss mechanisms.

Key Takeaways:

Conduction Loss is driven by current squared ( $I_{l o a d}^{2}$ ) and is independent of frequency. It dominates at high loads and low frequencies.
Switching Loss is driven by a combination of voltage, current, and frequency ( $V_{b u s} \times I_{l o a d} \times f_{s w}$ ).
Gate Drive Loss is driven primarily by frequency ( $f_{s w}$ ).
The desire to increase switching frequency for higher power density is in direct conflict with efficiency, as switching and gate drive losses become dominant.

This concludes our module on "The Hard Switching Problem." We have fully defined why hard switching is inefficient and noisy, and we now understand how those problems scale with the converter's operating conditions.

We are now perfectly positioned to explore the solution. In our next lesson, we will begin the next module by formally defining zero voltage switching (ZVS) and explaining how using a resonant network of inductors and capacitors can eliminate the turn-on switching loss, breaking the punishing trade-off between frequency and efficiency.

Recommended resources