Building a Ripple-Carry Adder

The Logic of Multi-Bit Addition

Think about how you add multi-digit numbers on paper, like 18 + 24. You start from the rightmost column (the least significant digits):

1. Add 8 + 4 to get 12. You write down the 2 and carry over the 1.
2. Move to the next column. You add 1 + 2 plus the 1 you carried over, getting 4.
3. The final result is 42.

Binary addition works exactly the same way. The carry-out from adding one pair of bits becomes the carry-in for the next pair. A circuit that mimics this process is called a ripple-carry adder because the carry signal "ripples" from one stage to the next.

The video below explains and visualizes how you can "daisy-chain" the Full Adders you built in the previous lesson to create this effect.

The Architecture of a 4-Bit Adder

To build a 4-bit adder, which adds two 4-bit numbers (let's call them A and B), we will need four Full Adder circuits. Let's denote the bits of A as $A_3{A}_2{A}_1{A}_0$ and the bits of B as $B_3{B}_2{B}_1{B}_0$.

Here is the high-level architecture:

A 4-bit ripple-carry adder built from four Full Adder blocks. The carry-out (Cout) from each stage is connected to the carry-in (Cin) of the next stage, from right to left (LSB to MSB).

Let's break down the connections shown in this diagram:

• Stage 0 (LSB): The first Full Adder on the right adds the least significant bits, $A_0$ and $B_0$. Its carry-in is tied to 0 because there is no preceding calculation. It produces sum bit $S_0$ and a carry-out $C_1$.
• Stage 1: The second Full Adder adds bits $A_1$ and $B_1$, along with the carry-in from the previous stage, $C_1$. It produces sum bit $S_1$ and a new carry-out $C_2$.
• Stage 2: The third Full Adder adds $A_2$, $B_2$, and the incoming carry $C_2$. It produces sum bit $S_2$ and carry-out $C_3$.
• Stage 3 (MSB): The final Full Adder adds the most significant bits, $A_3$ and $B_3$, along with the carry $C_3$. It produces the final sum bit $S_3$ and the overall carry-out of the entire 4-bit addition, $C_{out}$.

The final 4-bit sum is represented by the collection of the sum outputs: $S_3{S}_2{S}_1{S}_0$. The final $C_{out}$ is also very important; it tells us if the addition resulted in a value too large to be represented by 4 bits (an "overflow").

The following video provides a fantastic, detailed walkthrough of this exact process, showing each connection and explaining the flow of data.

Building the Circuit

Now that you understand the architecture, let's dive into the details of building it. The following article provides a concise guide and also introduces a critical real-world concept: propagation delay.

The design's modularity is its main strength. You can see this clearly in hardware description languages (HDLs), which are used to design real chips. The following article shows HDL code for a 16-bit adder. You don't need to understand the syntax, but look at the PARTS section to see the beautiful, repetitive pattern of chaining Full Adders.

Here is what a 4-bit ripple-carry adder looks like when you zoom in and see all the individual logic gates you've learned about. This is the culmination of everything you've done so far in this module.

A complete circuit diagram of a 4-bit ripple-carry adder. Each block of gates represents one of the Full Adders from our block diagram, all wired together to add two 4-bit numbers.

A Look Ahead: The Problem with Rippling

The DigiSim.io article you read mentioned a key drawback: propagation delay. The final stage (the MSB) cannot produce a correct sum until the carry from the first stage has "rippled" all the way through the chain. For a 4-bit adder, this is quick. But for a 64-bit adder in a modern CPU, this delay would be far too long.

This physical limitation is a core challenge in CPU design. While the ripple-carry adder is logically correct, faster (and more complex) designs like the Carry-Lookahead Adder were invented to solve this problem. We won't build one in this course, but it's important to understand that every design choice has trade-offs, in this case, simplicity versus speed.

Conclusion

You have now successfully designed a circuit capable of multi-bit arithmetic. By chaining together the Full Adders you mastered in the previous lesson, you've created a functional 4-bit ripple-carry adder.

Here are the key takeaways from this lesson:

• A multi-bit adder can be constructed by chaining together multiple Full Adder blocks.
• In a ripple-carry adder, the carry-out from each stage is fed as the carry-in to the subsequent stage.
• The first stage (LSB) has its carry-in set to 0. The final carry-out from the last stage (MSB) indicates an unsigned overflow.
• This design is simple and modular, but its speed is limited by the propagation delay of the carry signal as it "ripples" through the chain.

You now have the "addition" part of your future Arithmetic Logic Unit. In the next lesson, we will build the "logic" part—a unit for performing bitwise operations like AND and NOT on multi-bit numbers.