Welcome back! In our last lesson, you successfully built a NOT gate, your first piece of digital logic, by using a single transistor as an electronic switch. This was a crucial first step in bridging the gap between the flow of electrons and the logic that powers computation.
Today, we'll build upon that foundation to construct one of the most important components in all of digital electronics: the NAND gate. The goal of this lesson is to construct a NAND gate using transistors in simulation. You'll discover why its output is 0 only when both its inputs are 1, and you'll build it using two different methods. This gate is a fundamental building block, not just for simple circuits, but for the very CPU you aim to design.
What is a NAND Gate?
The name "NAND" is a contraction of "Not AND". As the name implies, its function is equivalent to performing an AND operation and then inverting the result with a NOT operation. Given your C programming background, you can think of it as !(A && B).
The gate has two inputs (A and B) and one output (Y). Its behavior is defined by the following truth table:
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Notice that the output is HIGH (1) for every input combination except when both A and B are HIGH (1).
Building a NAND Gate with NPN Transistors
Let's start with an approach that builds directly on what you learned in the last lesson. We used a single NPN transistor to create a NOT gate that could pull the output LOW. What happens if we place two of these transistor switches in a line?
The core idea is that to pull the output LOW, we need to create an uninterrupted path from the output terminal to ground. If we connect two NPN transistors in series, both of them must be switched ON simultaneously to complete this path.
This image shows exactly such a circuit, known as a Resistor-Transistor Logic (RTL) NAND gate.
Let's walk through how it works:
- The output is connected to the power supply (
+Vcc) through a pull-up resistor (R2). This means the output will be HIGH by default, unless something actively pulls it LOW. - The two transistors,
T1andT2, are connected in series between the output and ground. - If A is 0 or B is 0 (or both are 0): At least one transistor will be OFF, acting as an open switch. This breaks the path to ground. The pull-up resistor
R2successfully pulls the output HIGH (1). - Only when A is 1 AND B is 1: Both transistors turn ON, acting as closed switches. This completes the path from the output, through both transistors, to ground. The output voltage is pulled LOW (0).
This physical behavior perfectly matches the NAND truth table. To get a more detailed explanation of this circuit, you can read the following guide.
Logic Gates Using Transistors As Saturated Switches
This article from Electronics Tutorials provides a clear breakdown of building logic gates using Resistor-Transistor Logic (RTL), which is the method we are examining here.
Please read the sections titled "The RTL NAND Logic Gate Using Transistors" and the explanation directly following the "RTL NAND Gate Circuit" diagram. This will reinforce your understanding of how the series transistor configuration achieves the NAND function.
The Modern Approach: CMOS NAND Gate
The RTL design works perfectly, but it has a drawback: when the output is LOW, there's a constant flow of current from +Vcc, through the resistor R2, and through the transistors to ground. This wastes energy. Modern computers, from your phone to supercomputers, rely on a much more power-efficient technology called CMOS (Complementary Metal-Oxide-Semiconductor).
CMOS logic uses two complementary types of transistors:
- NMOS (n-type MOS): Behaves like the NPN transistors we've been using. It turns ON when its input is HIGH (1).
- PMOS (p-type MOS): Behaves in the opposite way. It turns ON when its input is LOW (0).
By cleverly combining these, we can build gates that consume almost no power when their state is not changing. The following video gives an excellent high-level overview of how these transistors are the "Lego bricks" of a modern CPU.
How do Transistors Build into a CPU? 🖥️🤔 How do Transistors Work? 🖥️🤔
This video from Branch Education beautifully visualizes how N-Type and P-Type transistors work and how they are combined to form logic gates within a CPU.
First, watch the section explaining the N-Type and P-Type transistors. This will clarify their complementary nature. Then, jump to the excellent animation showing the construction of a NAND gate. Pay close attention to the arrangement: the P-Types are in parallel, and the N-Types are in series.
As you saw in the video, a CMOS NAND gate is constructed as follows:
Let's break down this elegant structure:
- The Pull-Up Network (PMOS in parallel): The two PMOS transistors are connected in parallel between the power supply (3.3v) and the output (Y). Since PMOS transistors turn ON with a LOW input, if either input A or input B is LOW, at least one of the PMOS transistors will switch ON, creating a path from the power supply to the output. This pulls the output HIGH (1).
- The Pull-Down Network (NMOS in series): The two NMOS transistors are connected in series between the output (Y) and ground. Since NMOS transistors turn ON with a HIGH input, both input A and input B must be HIGH to switch both transistors ON. Only then is a path to ground created, pulling the output LOW (0).
This design is highly efficient. In any stable state (00, 01, 10, or 11), there is never a direct path from the power supply to ground, preventing wasted energy.
To see this in action step-by-step, the next video walks through each input combination for a CMOS NAND gate.
Building logic gates from MOSFET transistors
This video from EngMicroLectures provides a detailed, whiteboard-style walkthrough of a CMOS NAND gate's operation, tracing the logic for every possible input.
Watch the section that specifically analyzes the NAND gate circuit. The lecturer methodically applies inputs 00, 01, 10, and 11 and shows which transistors turn on or off to produce the correct output.
Finally, let's get hands-on. The following resource contains an interactive simulation where you can control the inputs to a CMOS NAND gate and observe the result.
Making Logic Gates from Transistors - Antares
This article by Andreas Fleischmann features several interactive circuit simulations. We will use the final one for the CMOS NAND gate.
Scroll down to the section titled "CMOS NAND Gate". You will find a complete circuit diagram and an embedded Falstad simulation. Start the simulation and click the switches for inputs A and B to verify the NAND truth table for yourself. Observe how the current (yellow dots) only flows to the output, and never directly from power to ground.
Conclusion
You have now successfully constructed a NAND gate, a cornerstone of digital logic. You've seen two ways to do it: the conceptually simpler RTL method using series transistors, and the power-efficient CMOS method that powers virtually all modern electronics.
Let's summarize the key takeaways:
- A NAND gate implements the
!(A && B)function. Its output is LOW if and only if both inputs are HIGH. - An RTL NAND gate can be built with two NPN transistors in series forming a pull-down network, with a single pull-up resistor.
- A CMOS NAND gate uses a pull-up network of PMOS transistors in parallel and a pull-down network of NMOS transistors in series. This complementary design is extremely power-efficient.
You are now firmly moving up the ladder of abstraction. We started with transistors, built a NOT gate, and now a NAND gate. In the next lesson, we will discover the true power of the NAND gate. You will learn how it is a "universal gate," meaning we can construct every other basic logic gate (NOT, AND, OR) using only NAND gates. This powerful concept is what allows us to build immensely complex CPUs from a very small set of repeating components.