NVIC Architecture and Configuration

1. The NVIC Architecture: An Overview

The NVIC acts as a centralized gatekeeper or arbitrator for all peripheral interrupts. It receives interrupt requests from peripherals like timers, UARTs, and GPIOs, and decides which ones get passed along to the processor core based on their configuration.

The name "Nested Vectored Interrupt Controller" perfectly describes its function:

• Vectored: As we learned previously, the NVIC provides a unique exception number (or "vector") for each interrupt source. The processor uses this number to look up the correct handler address in the vector table.
• Nested: This is a key feature. The NVIC manages a priority system that allows a more urgent interrupt to preempt (i.e., interrupt) a less urgent, currently running interrupt handler. We will touch upon the configuration of priority here, and dive deep into the strategies for managing nesting and preemption in the next lesson.

2. Configuring the NVIC: The Control Registers

The entire behavior of the NVIC is controlled through a set of memory-mapped registers located in the System Control Space (SCS). As a driver developer, you'll interact with these registers constantly. A solid understanding of them is essential.

Let's start with a comprehensive overview of the key registers.

To reinforce what you've just read, let's summarize the purpose of these register groups. Each group is an array of 32-bit registers, where each bit or byte corresponds to a specific IRQ number.

• Interrupt Set-Enable (NVIC_ISERx) & Clear-Enable (NVIC_ICERx)

  • Purpose: To enable or disable an interrupt in the NVIC.
  • How it works: Writing a 1 to bit n of an NVIC_ISER register enables IRQ n. Writing a 1 to the corresponding bit in an NVIC_ICER register disables it. Reading ISER tells you which interrupts are currently enabled.

• Interrupt Set-Pending (NVIC_ISPRx) & Clear-Pending (NVIC_ICPRx)

  • Purpose: To manage the "pending" state of an interrupt. An interrupt is pending if the request has been received but the CPU has not yet started executing its handler.
  • How it works: You can read ISPR to see which interrupts are pending. You can write to ICPR to clear a pending state, which might be necessary if the condition causing the interrupt has already been handled. Writing to ISPR allows you to trigger an interrupt from software, which is extremely useful for testing ISRs.

• Interrupt Priority Registers (NVIC_IPRx)

  • Purpose: To assign a priority level to each interrupt. This is the most important configuration for managing real-time behavior.
  • How it works: This is an array of 8-bit registers. Each IRQ has one 8-bit field to define its priority. We'll explore this in detail next.

• Interrupt Active Bit Registers (NVIC_IABRx) (Not on Cortex-M0/M0+)

  • Purpose: To check which interrupt is currently active (i.e., its ISR is running).
  • How it works: This is a read-only register bank. If bit n is 1, it means IRQ n is currently being serviced.

3. A Deep Dive into Priority Configuration

Setting interrupt priorities is fundamental to building a stable and responsive system. There are a few key rules and "gotchas" you must understand.

Let's crystallize those two critical points:

1. Inverted Priority Logic: In the ARM world, a lower numerical value means a higher logical priority (urgency). Priority 0 is the highest urgency, priority 1 is next, and so on. This is a very common source of confusion and a frequent interview question.

2. Vendor-Specific, Left-Aligned Priority Bits: Although each interrupt has an 8-bit priority register field, microcontroller vendors only implement a certain number of these bits (e.g., 3 bits for 8 priority levels, or 4 bits for 16 levels). To maintain compatibility, these implemented bits are always the most-significant (left-most) ones. This means that to set a priority level of 3 on a system with 4 implemented bits, you don't write 0x03. You write 0x30.

4. The Complete Configuration Flow

Enabling an interrupt is a two-part process that involves configuring both the peripheral itself and the NVIC.

The standard sequence is:

1. Set Priority (NVIC): Configure the interrupt's priority level in the appropriate NVIC_IPR register. It's good practice to do this before enabling the interrupt to avoid it firing with a default priority of 0.
2. Enable Interrupt (Peripheral): Set the specific bit in the peripheral's own control registers that allows it to generate interrupt requests. For example, a UART peripheral will have a "Receive Interrupt Enable" bit.
3. Enable Interrupt (NVIC): Set the corresponding bit in the NVIC_ISER register to allow the NVIC to pass the interrupt to the CPU.

Let's see this in action. The following video demonstrates this exact workflow using a high-level configuration tool (STM32CubeMX) and shows the resulting code.

Interview Preparation

Being able to clearly articulate how the NVIC works is crucial in an interview for a driver development role.

• Question: "What are the essential steps to enable a peripheral interrupt, for example, from a UART?"

  • Your Answer: "It's a three-step process. First, I would set the interrupt's priority in the NVIC's Interrupt Priority Register (IPR). Second, I'd configure the UART peripheral itself by setting the relevant interrupt enable bit in its control register—for instance, the 'Receive Interrupt Enable' bit. Finally, I would enable the interrupt in the NVIC by setting its corresponding bit in the Interrupt Set-Enable Register (ISER). All three steps are required."

• Question: "What is a common pitfall when configuring interrupt priorities on an ARM Cortex-M processor?"

  • Your Answer: "A common mistake is forgetting that the priority system is inverted—a lower number means a higher priority. Another is not accounting for the fact that priority bits are left-aligned in the 8-bit IPR field. For a system with, say, 4 priority bits, setting the priority to level 5 requires writing 0x50, not 0x05."

• Question: "How would you trigger an interrupt from software for testing purposes, and why would you do that?"

  • Your Answer: "You can trigger any peripheral interrupt in software by writing a 1 to its corresponding bit in the NVIC's Interrupt Set-Pending Register (ISPR). This is incredibly useful for unit testing an Interrupt Service Routine in isolation, without having to set up the physical hardware conditions to make the peripheral generate the interrupt."

Conclusion

In this lesson, we've pulled back the curtain on the NVIC. You now understand its architecture and, more importantly, the specific registers used to configure it.

Key Takeaways:

• The NVIC is the central controller for all external (peripheral) interrupts.
• Its behavior is governed by several key register sets: ISER/ICER (enabling), ISPR/ICPR (pending status), and IPR (priority).
• Enabling an interrupt is a multi-step process involving both the peripheral and the NVIC.
• Priority configuration is critical and has two main quirks: inverted numbering (0 is highest) and left-aligned bits.

Next Lesson Preview:
We've learned how to set priorities. The next logical step is to understand the consequences of those settings. In our next lesson, we will focus on how the NVIC uses your priority configuration to manage preemption, allowing more urgent tasks to interrupt less urgent ones. We will also explore the advanced feature of priority grouping to gain even finer control over real-time behavior.