Embedded Systems Engineering

Set up a Windows-friendly Arm GNU/STM32 workflow and run a provided simulator smoke test for the course-selected Cortex-M target and required peripherals.

Build, flash into the simulator, and debug a minimal C firmware project using breakpoints, single-stepping, and register inspection.

Use fixed-width integer types to predict the results of signed, unsigned, and integer-promotion operations in embedded C.

Use bit masks, shifts, and bitwise operators to extract and modify individual register fields.

Use pointers to read and write specified memory locations safely in a small embedded C program.

Apply const, volatile, and static correctly, and explain why volatile alone does not make interrupt-shared state atomic or race-free.

Implement a fixed-capacity collection of structured records using arrays, structs, enums, and functions.

Organize a small firmware project into source and header files, then resolve representative include, undefined-symbol, and duplicate-symbol diagnostics.

Identify the Cortex-M core, buses, memories, and STM32 peripherals in a microcontroller block diagram.

Use an STM32 datasheet and reference manual to locate a peripheral base address, register layout, and bit-field definition.

Determine how access width, alignment, and little-endian byte order map a multibyte value into Cortex-M memory.

Translate a peripheral address and register offset into a typed memory-mapped register access.

Trace the sequence from processor reset through the vector table, startup code, data initialization, and main.

Explain how the stack pointer, program counter, link register, and general-purpose registers change during a C function call.

Classify code, read-only data, initialized data, zero-initialized data, heap, and stack in a linker map.

Inspect an ELF firmware file to find sections, symbols, addresses, and disassembled instructions.

Derive the core and peripheral clock frequencies from a specified STM32 clock-tree configuration.

Enable and reset an STM32 peripheral through the appropriate RCC registers.

Configure a GPIO pin's mode, output type, speed, and pull resistors through register-level code.

Drive and toggle a simulated LED using atomic GPIO set/reset operations.

Read a simulated digital input and explain the effects of pull-up and pull-down configurations.

Configure a GPIO pin for a specified alternate function using the reference manual.

Write a reusable register-level GPIO driver with explicit configuration and argument validation.

Verify GPIO register writes and pin transitions using debugger and simulator traces.

Trace Cortex-M exception entry and return, including automatic stack-frame creation.

Install an interrupt handler in the vector table and clear its peripheral interrupt source correctly.

Configure NVIC enable bits and priority fields for a specified interrupt policy.

Apply Cortex-M priority grouping and preemption rules to predict which pending interrupt executes first.

Implement nonblocking switch debouncing using a periodic SysTick-derived time base.

Configure a general-purpose timer to produce a specified update period from its input clock.

Generate a PWM waveform with a specified frequency and duty cycle using timer output compare.

Measure simulated interrupt latency and execution time using timer values or trace timestamps.

Calculate UART baud-rate register settings and quantify the resulting baud error.

Implement polling-based UART transmission and reception through STM32 registers.

Implement interrupt-driven UART reception using a fixed-size ring buffer.

Safely share ring-buffer state between foreground code and the UART interrupt handler using a justified single-producer/single-consumer or critical-section design.

Detect and recover from UART framing, parity, noise, and overrun conditions.

Design a length-delimited or framed serial message format with an integrity check.

Implement a nonblocking state-machine parser for fragmented serial input.

Use structured UART logs to isolate a fault in simulated firmware.

Interpret an SPI timing diagram in terms of clock polarity, clock phase, bit order, and chip select.

Configure an STM32 SPI peripheral for a specified device transaction.

Implement a blocking SPI register-read and register-write driver for a simulated peripheral.

Add timeout and status checking to an SPI transaction.

Interpret an I2C transaction containing START, address, ACK/NACK, repeated START, data, and STOP conditions.

Configure an STM32 I2C peripheral for a specified bus speed and target address.

Implement an I2C register-read transaction for a simulated sensor.

Use a protocol trace to diagnose an incorrect SPI or I2C transaction.

Relate ADC resolution, reference voltage, quantization, and sample time to measurement accuracy.

Configure an STM32 ADC channel and acquire a single simulated conversion by polling.

Convert an ADC code into a physical voltage using calibration parameters.

Trigger ADC conversions periodically from a hardware timer.

Configure DMA to transfer peripheral samples into a memory buffer without per-sample CPU intervention.

Implement circular DMA buffering with half-transfer and transfer-complete events.

Prevent inconsistent reads when foreground code processes a DMA-updated buffer.

Compare polling, interrupt-driven, and DMA-based acquisition by CPU cost and latency.

Construct a cooperative superloop scheduler that runs periodic activities without blocking delays.

Represent a reactive peripheral workflow as an explicit finite-state machine.

Assign timing budgets to superloop activities and determine whether the loop meets its deadline.

Configure and service a watchdog so that stalled firmware causes a controlled reset.

Use sleep-on-idle safely without losing an interrupt event between checking work and sleeping.

Capture and decode a Cortex-M HardFault stack frame to identify the faulting instruction.

Separate hardware-dependent drivers from hardware-independent application logic through C interfaces.

Write host-side unit tests for a hardware-independent state machine or protocol parser.

Distinguish hard, firm, and soft real-time requirements using concrete embedded-system failures.

Model a periodic task using execution time, period, deadline, priority, and release jitter.

Measure an observed worst-case execution time for a firmware routine in the simulator and explain why it is not a hardware WCET guarantee.

Apply rate-monotonic utilization analysis to a small periodic task set and distinguish a sufficient result from an inconclusive one.

Determine whether a small task set is schedulable under earliest-deadline-first scheduling.

Explain priority inversion by tracing a schedule containing high-, medium-, and low-priority tasks.

Perform fixed-priority response-time analysis, including interference and a supplied blocking term, for a small task set.

Choose whether a time-critical activity belongs in an interrupt handler, deferred handler, or scheduled task.

Configure and build FreeRTOS for the simulated STM32 Cortex-M target.

Configure the RTOS tick rate and maximum system-call interrupt priority for specified timing and ISR requirements.

Create statically allocated tasks with specified priorities and stack sizes.

Trace a task through running, ready, blocked, and suspended states.

Use periodic delay-until semantics to prevent long-term drift in a real-time task.

Exchange typed data between tasks using a bounded FreeRTOS queue.

Signal a task efficiently from another task using a direct-to-task notification.

Measure task execution and CPU utilization using FreeRTOS run-time statistics or trace data.

Reproduce and explain a race condition caused by unsynchronized access to shared state.

Protect a short shared-memory operation with an appropriately bounded critical section.

Use a mutex with priority inheritance to protect a shared resource.

Choose between a binary semaphore, counting semaphore, queue, and task notification for a synchronization requirement.

Call interrupt-safe RTOS APIs and request a context switch correctly from an ISR.

Construct a lock-order rule that prevents deadlock in a two-resource design.

Measure task stack headroom and select a justified stack allocation.

Design an overload policy for queue saturation, missed deadlines, or excessive interrupt rates.

Write measurable functional, timing, and fault-recovery requirements with acceptance criteria for a simulated STM32 sensor-and-control system.

Partition the capstone into drivers, interrupt services, RTOS tasks, communication paths, and application logic.

Create a timing and priority table from the capstone requirements.

Integrate timer-triggered ADC acquisition with circular DMA and an ISR-to-task notification to deliver completed sample blocks to a processing task.

Integrate a nonblocking serial command parser with the processing task through a bounded queue to control sampling parameters and transmit telemetry.

Verify task periods, interrupt latency, queue occupancy, and end-to-end response time against the requirements.

Inject communication, timing, and peripheral faults and verify the specified detection and recovery behavior using logs, debugger data, and trace evidence.

Produce a hardware bring-up and validation checklist that identifies what simulation could not verify.