Metrology

Define critical dimension, pitch, overlay, edge-placement error, film thickness, and defectivity.

Distinguish metrology, inspection, defect review, failure analysis, and process control.

Classify semiconductor measurements as inline, at-line, offline, destructive, or nondestructive.

Explain how a measurement signal can lead to process correction and yield improvement.

Identify why shrinking features and increasingly three-dimensional devices make metrology more difficult.

Explain the roles of reference standards, calibration, and traceability in semiconductor metrology.

Distinguish accuracy, precision, resolution, repeatability, and reproducibility.

Separate measurement bias, random variation, and process variation in a simple dataset.

Calculate a measurement result with a basic uncertainty interval.

Interpret trade-offs among sensitivity, field of view, sampling density, throughput, and wafer damage.

Interpret a basic gauge repeatability and reproducibility study.

Use a statistical process-control chart to distinguish common-cause variation from a likely excursion.

Explain how wavelength and numerical aperture constrain lithographic resolution and depth of focus.

Trace the EUV patterning path from light source through reflective mask, projection optics, resist, and etch transfer.

Identify the measurement-critical functions of EUV masks, pellicles, resists, and underlayers.

Explain how photon statistics and resist chemistry produce stochastic patterning defects.

Compare conventional EUV and High-NA EUV in resolution, depth of focus, field size, and process complexity.

Explain how anamorphic imaging and half-field exposure affect High-NA EUV manufacturing.

Relate lithography-roadmap changes to emerging requirements for overlay, defect, and edge-placement metrology.

Explain how optical scatterometry infers feature geometry from measured light.

Identify how model assumptions can bias an optical scatterometry result.

Explain how CD-SEM images are converted into dimensional measurements.

Assess charging, contamination, edge-detection, and sampling limitations in electron-beam metrology.

Explain how atomic force microscopy reconstructs surface topography.

Compare TEM-based measurements with CD-SEM and AFM in resolution, sample preparation, and destructiveness.

Compare optical, electron-beam, and X-ray approaches to overlay and three-dimensional dimensional metrology.

Distinguish bright-field, dark-field, and patterned-wafer optical defect inspection.

Explain the sensitivity-throughput trade-off in electron-beam defect inspection.

Describe the role of actinic inspection and review for EUV mask defects.

Select an appropriate technique for measuring thin-film thickness, composition, or interface quality.

Explain how X-ray and electron tomography can reveal buried three-dimensional structures.

Relate sample preparation choices to artifacts in destructive failure analysis.

Match defect-inspection and materials-analysis methods to lithography, deposition, etch, and CMP use cases.

Identify the critical measurands for High-NA EUV process development and volume manufacturing.

Explain why EUV mask three-dimensional effects create a need for actinic and model-based metrology.

Design a sampling concept for estimating rare stochastic-defect rates.

Explain how critical dimension, overlay, and local variability combine into edge-placement error.

Assess the metrology implications of buried alignment marks and wafer distortion.

Compare metrology challenges posed by gate-all-around transistors, backside power delivery, and CFET structures.

Evaluate how throughput and data-volume constraints limit high-resolution wafer inspection.

Distinguish evidence-based lithography roadmaps from speculative post-EUV forecasts.

Explain the proposed resolution advantage and engineering challenges of beyond-EUV soft-X-ray lithography.

Assess the metrology implications of multibeam electron-beam direct-write lithography.

Assess the metrology implications of nanoimprint lithography for leading-edge patterning.

Assess the metrology implications of directed self-assembly and other self-aligned patterning methods.

Compare candidate post-EUV approaches by resolution, throughput, defectivity, infrastructure, and measurement burden.

Build a technology-readiness scorecard for a post-EUV patterning and metrology concept.

Map the semiconductor-metrology value chain across components, instruments, software, services, and standards.

Classify incumbent and emerging suppliers by the measurement problems they address.

Explain how fab qualification cycles shape time to revenue for a new metrology product.

Assess how installed base, process recipes, reference data, and service networks create switching costs.

Compare hardware sales, recurring service, consumables, and software revenue models in metrology.

Construct a bottom-up estimate of the addressable market for a narrowly defined metrology use case.

Identify supply-chain concentration, export-control, and customer-concentration risks for a metrology company.

Translate a startup's technical claim into measurable performance and customer-value metrics.

Construct a benchmark table comparing a proposed metrology product with incumbent alternatives.

Design a proof-of-concept test that separates genuine tool performance from a favorable demonstration.

Assess technology readiness across prototype stability, manufacturability, calibration, and fab integration.

Evaluate whether patents, know-how, proprietary datasets, and workflow integration support a defensible moat.

Assess whether the team and supplier plan cover the scientific, engineering, service, and manufacturing requirements.

Identify technical and commercial red flags in a metrology company's diligence materials.

Define the customer pain point and purchasing stakeholder for a metrology investment opportunity.

Estimate unit economics and capital requirements for a metrology hardware company.

Construct adoption scenarios that reflect qualification time, wafer-fab cycles, and customer concentration.

Evaluate competitive advantage using performance, throughput, cost of ownership, and integration evidence.

Build a risk register covering technical, market, financing, regulatory, and supply-chain risks.

Define milestone-based financing gates for technical validation and commercial scale-up.

Write an investment-committee memo for a private semiconductor-metrology opportunity.