FPGA Design and Verification

Build and program a minimal iCEBreaker design using Yosys, nextpnr-ice40, icepack, and iceprog.

Map top-level HDL ports to iCEBreaker pins with a PCF physical-constraints file.

Run a SystemVerilog module in Icarus Verilog and inspect its behavior in a waveform viewer.

Interpret synthesis and place-and-route reports for warnings, resource use, maximum clock frequency, and unconstrained paths.

Organize HDL sources, constraints, simulations, and build outputs in a reproducible project structure.

Diagnose a failed FPGA build by isolating errors from synthesis, constraints, place-and-route, or programming.

Distinguish conventional RTL HDLs such as SystemVerilog and VHDL from hardware-construction languages such as Chisel, SpinalHDL, Amaranth, and Bluespec, and identify why a team might choose each category.

Implement combinational logic with always_comb while avoiding inferred latches.

Implement resettable clocked state with always_ff and nonblocking assignments.

Predict how expression width, signedness, truncation, and extension affect synthesized arithmetic.

Create parameterized modules with type-safe widths and elaboration-time validity checks.

Use generate constructs to elaborate configurable hardware structures.

Encode and implement a finite-state machine with explicit legal transitions and recovery behavior.

Infer an iCE40 block RAM from a portable synchronous-memory description and confirm the inferred resource in a synthesis report.

Read a small VHDL RTL module and identify its ports, generics, combinational logic, and clocked state.

Apply ready/valid handshake rules to transfer data without loss or duplication.

Implement a one-stage elastic buffer that handles backpressure.

Implement a parameterized synchronous FIFO with full, empty, and occupancy status.

Implement a fair arbiter for multiple producers sharing one consumer.

Route transactions through a parameterized stream multiplexer and demultiplexer.

Extract and insert fixed-format headers and footers in a streaming pipeline.

Implement a streaming CRC accumulator and use it to generate and check frame trailers.

Implement an LFSR pattern generator and a self-checking pattern receiver.

Write a clocked SystemVerilog testbench with deterministic reset and stimulus sequencing.

Turn an expected-value model into automatic pass/fail checks in a testbench.

Test boundary values and create compile-fail cases for invalid parameter configurations.

Apply randomized transaction timing and backpressure jitter with $urandom_range to expose sequencing defects.

Create a bus functional model with transaction-level driver and monitor tasks.

Build a cocotb test that drives a DUT and checks transactions against a Python reference model.

Use Verilator for fast compiled simulation of a synthesizable subsystem.

Triage an injected RTL defect using lint findings, targeted assertions, and waveform evidence.

Calculate setup and hold timing margins for a register-to-register path.

Write primary and generated clock constraints and confirm that the selected timing analyzer recognizes them.

Derive and write a set_input_delay constraint from an external device timing specification.

Derive and write a set_output_delay constraint from an external device timing specification.

Interpret critical-path, slack, and path-segmentation information in a static timing report.

Improve a failing synchronous path by pipelining or restructuring its logic.

Justify each set_false_path or multicycle-path exception and distinguish valid exceptions from ones that conceal design errors.

Explain the effect of clock-group constraints and use unconstrained-path reports to audit timing coverage.

Classify a clock-domain crossing as a level, event, multi-bit control transfer, or data stream and select an appropriate crossing structure.

Implement a two-flop synchronizer for a single-bit level signal and explain how it reduces metastability risk.

Transfer a single-cycle event between unrelated clock domains with a toggle synchronizer.

Transfer a stable multi-bit control word between clock domains with a request/acknowledge handshake.

Explain why independently synchronizing the bits of a changing data bus is unsafe.

Trace Gray-coded pointers through an asynchronous FIFO architecture.

Integrate a reviewed asynchronous FIFO implementation and verify it under unrelated clocks, wraparound, full, and empty conditions.

Implement asynchronous assertion with synchronized reset deassertion and identify reset-domain-crossing hazards.

Implement a single-master Wishbone transaction and explain its request, acknowledgement, and error signals.

Create a Wishbone-controlled register peripheral with read-only, read-write, and write-one-to-clear fields.

Generate an HDL register block and software-visible register description from a SystemRDL specification.

Connect a control-register interface to a ready/valid streaming datapath.

Implement an adapter between two interfaces with different backpressure or response rules.

Read an AXI4-Lite timing trace and identify valid and invalid channel handshakes.

Compare the intended use of AXI4-Lite, APB, AHB-Lite, Avalon-MM, and Wishbone.

Define a stable internal control and streaming interface that isolates application logic from external protocols.

Synchronize and debounce an asynchronous board-level input before using it in synchronous logic.

Implement and simulate a configurable UART transmitter.

Implement and simulate a UART receiver with start-bit validation and framing-error detection.

Implement an SPI master transaction engine with configurable clock polarity and phase.

Implement a basic I²C master transfer with open-drain signaling and acknowledgement checking.

Write a behavioral SystemVerilog model of an SPI slave peripheral to verify SPI master transactions.

Write a behavioral SystemVerilog model of an I²C slave peripheral with open-drain ACK/NACK signaling to verify I²C master transfers.

Write a Python host utility that exchanges framed commands and data with the FPGA over UART.

Specify a framed UART command protocol for register access and streamed payloads.

Implement a parser that converts validated UART frames into internal control or stream transactions.

Connect control registers, a FIFO, a processing stage, and a CRC checker into a backpressured pipeline.

Add error counters and status registers that make dropped, malformed, and corrupted frames observable.

Build a self-checking end-to-end simulation of the UART-controlled pipeline.

Diagnose an FPGA-to-peripheral communication failure using waveforms, loopback tests, and observable debug signals.

Deploy the pipeline to the iCEBreaker and validate it with an automated Python test.

Specify a reusable transaction interface between sensor-control logic and an SPI or I²C engine.

Implement a sequencer that configures and periodically samples a simulated sensor.

Attach a free-running sample counter to sensor readings and buffer the timestamped samples through UART backpressure.

Implement a configurable fixed-point moving-average filter stage for sensor samples.

Build a self-checking simulation using a behavioral sensor model and injected protocol faults.

Run the acquisition design on the iCEBreaker with either a connected peripheral or a loopback substitute.

Represent sampled signals in signed fixed-point in-phase and quadrature form.

Generate quantized coefficients for a small FIR filter with a Python script.

Implement a pipelined FIR filter using fixed-point arithmetic.

Map framed bits to fixed-point BPSK symbols and recover bits from noiseless samples with a hard-decision detector.

Add frame synchronization, payload length, and CRC checking to a digital communications stream.

Build a self-checking transmitter-channel-receiver loopback simulation with injected bit errors.

Deploy a reduced-rate communications loopback on the iCEBreaker and inspect live error statistics.

Design an address map and interconnect for multiple reusable Wishbone peripherals.

Integrate the previously verified UART-control and sensor-acquisition blocks behind common Wishbone and ready/valid interfaces.

Add run-time selection between pass-through and previously developed processing stages, then verify end-to-end routing.

Automate lint, simulation, synthesis, timing checks, and bitstream generation with a single build entry point.

Run reproducible FPGA checks in continuous integration using a pinned open-source tool environment.

Compare alternative implementations using resource, throughput, latency, and timing measurements.

Package an RTL block with its constraints, tests, interface documentation, and software access example for reuse.

Explain when external DDR or high-speed serial links require vendor IP, and outline the bring-up and verification plan for migrating such a design to a capable FPGA platform.