Concurrency and Memory Ordering Across Firmware and Drivers

Correct a volatile-only C shared-state example with C11 atomic operations and explain why volatile does not provide inter-thread synchronization.

Analyze an acquire-release memory-ordering trace and determine which outcomes are permitted on a weakly ordered processor.

Select an appropriate synchronization primitive—mutex, spinlock, semaphore, completion/event, or atomic operation—for a given thread and interrupt-context scenario.

Place and justify compiler, CPU-memory, and device-I/O barriers in an MMIO or DMA ownership-transfer sequence, distinguishing memory ordering from cache coherency.